EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 272

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Figure 7–32. Stratix IV IOE Output and Output-Enable Path Registers
Notes to
(1) You can bypass each register block of the output and output-enable paths.
(2) Data coming from the FPGA core are at half the frequency of the memory interface clock frequency in half-rate mode.
(3) The half-rate clock comes from the PLL, while the alignment clock comes from the write-leveling delay chains.
(4) These registers are only used in DDR3 SDRAM interfaces for write-leveling purposes.
(5) The write clock can come from either the PLL or from the write-leveling delay chain. The DQ write clock and DQS write clock have a 90° offset between them.
Figure
Half-Rate Clock (3)
7–32:
From Core (2)
From Core (2)
(wdata2) (2)
(wdata0) (2)
(wdata3) (2)
(wdata1) (2)
From Core
From Core
From Core
From Core
Half Data Rate to Single Data Rate Output-Enable Registers
D
D
D
D
D
D
DFF
DFF
Half Data Rate to Single Data Rate Output Registers
DFF
DFF
DFF
DFF
Q
Q
Q
Q
Q
Q
Alignment
Clock (3)
D
D
D
DFF
DFF
DFF
Q
Q
Q
0
1
0
1
0
1
D
D
D
DFF
DFF
DFF
(Note 1)
Q
Q
Q
D
D
D
DFF
DFF
DFF
Q
Q
Q
Alignment Registers (4)
Alignment Registers (4)
D
D
D
DFF
DFF
DFF
Q
Q
Q
Clock (5)
Write
DFF
DFF
Output Reg Bo
Double Data Rate Output-Enable Registers
OE Reg B
Output Reg Ao
DFF
OE Reg A
DFF
D
D
D
D
Double Data Rate Output Registers
Q
Q
Q
Q
OE
OE
1
0
1
0
OR2
TRI
DQ or DQS