EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 315

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
February 2011 Altera Corporation
f
1
1
4. Select the LVDS receiver serial input ports (from the list) according to the input
5. In the Set Input Delay window, set the appropriate values in the Input Delay
6. Click Run to incorporate these values in the TimeQuest Timing Analyzer.
7. Assign the appropriate delay for all the LVDS receiver input ports following these
If no input delay is set in the TimeQuest Timing Analyzer, the receiver
channel-to-channel skew (RCCS) defaults to zero. You can also directly set the input
delay in a Synopsys Design Constraint file (.sdc) using the set_input_delay
command.
For more information about .sdc commands and the TimeQuest Timing Analyzer,
refer to the
Development Software Handbook.
Example 8–2
Example 8–2. RSKM
Data Rate: 1 Gbps, Board channel-to-channel skew = 200 ps
For Stratix IV devices:
TCCS = 100 ps (pending characterization)
SW = 300 ps (pending characterization)
TUI = 1000 ps
Total RCCS = TCCS + Board channel-to-channel skew= 100 ps + 200 ps
= 300 ps
RSKM= TUI - SW - RCCS
= 1000 ps - 300 ps - 300 ps
= 400 ps > 0
Because the RSKM > 0 ps, receiver non-DPA mode must work correctly.
You can also calculate RSKM using the steps described in
Enabled Differential Channels” on page
delay you set. Click OK.
Options section and Delay value.
steps. If you have already assigned Input Delay and you need to add more delay
to that input port, use the Add Delay option in the Set Input Delay window.
Quartus II TimeQuest Timing Analyzer
shows the RSKM calculation.
8–38.
chapter in volume 3 of the Quartus II
“Guidelines for DPA-
Stratix IV Device Handbook Volume 1
8–37