EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 284

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–6
Table 8–5. LVDS Channels Supported in Stratix IV GX Device Row I/O Banks
Stratix IV Device Handbook Volume 1
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
EP4SGX290
Device
28 Rx or eTx +
28 Rx or eTx +
28 Rx or eTx +
28 Rx or eTx +
FineLine BGA
28 Tx or eTx
28 Tx or eTx
28 Tx or eTx
28 Tx or eTx
780-Pin
—
Table 8–3
supported in Stratix IV GT devices.
Table 8–3. LVDS Channels Supported in Stratix IV GT Device Row I/O Banks
Table 8–4. LVDS Channels Supported in Stratix IV GT Device Column I/O Banks
Table 8–5
supported in Stratix IV GX devices.
(5)
Notes to
(1) Rx = true LVDS input buffers with OCT R
(2) The LVDS Rx and Tx channel count does not include dedicated clock input pins.
Notes to
(1) Rx = true LVDS input buffers without OCT R
(2) The LVDS Rx and Tx channel count does not include dedicated clock input pins.
EP4S100G2
EP4S100G3
EP4S100G4
EP4S100G5
LVDS_E_3R).
EP4S100G2
EP4S100G3
EP4S100G4
EP4S100G5
LVDS_E_3R).
EP4S40G2
EP4S40G5
EP4S40G2
EP4S40G5
Device
Device
Table
Table
and
and
28 Rx or eTx +
44 Rx or eTx +
44 Rx or eTx +
44 Rx or eTx +
FineLine BGA
28 Tx or eTx
44 Tx or eTx
44 Tx or eTx
44 Tx or eTx
1152-Pin
8–3:
8–4:
Table 8–4
Table 8–6
—
list the maximum number of row and column LVDS I/Os
46 Rx or eTx + 73 Tx or eTx
46 Rx or eTx + 73 Tx or eTx
46 Rx or eTx + 73 Tx or eTx
46 Rx or eTx + 73 Tx or eTx
list the maximum number of row and column LVDS I/Os
56 Rx or eTx +
56 Rx or eTx +
44 Rx or eTx +
44 Rx or eTx +
44 Rx or eTx +
FineLine BGA
1517-pin FineLine BGA
1517-pin FineLine BGA
56 Tx or eTx
56 Tx or eTx
44 Tx or eTx
44 Tx or eTx
44 Tx or eTx
96 Rx or eTx + 96 eTx
96 Rx or eTx + 96 eTx
96 Rx or eTx + 96 eTx
96 Rx or eTx + 96 eTx
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
1152-Pin
(4)
D
, eTx = emulated LVDS output buffers (either LVDS_E_1R or
—
—
—
—
D
, eTx = emulated LVDS output buffers (either LVDS_E_1R or
88 Rx or eTx +
88 Rx or eTx +
88 Rx or eTx +
FineLine BGA
88 Tx or eTx
88 Tx or eTx
88 Tx or eTx
1517-Pin
—
—
(Note
1), (2),
88 Rx or eTx +
FineLine BGA
88 Tx or eTx
47 Rx or eTx + 56 Tx or eTx
47 Rx or eTx + 56 Tx or eTx
47 Rx or eTx + 56 Tx or eTx
1760-Pin
128 Rx or eTx + 128 eTx
128 Rx or eTx + 128 eTx
128 Rx or eTx + 128 eTx
1932-pin FineLine BGA
1932-pin FineLine BGA
(3)
February 2011 Altera Corporation
—
—
—
—
(Part 1 of 2)
(Note
—
—
—
—
—
—
(Note
98 Rx or eTx +
FineLine BGA
1),
98 Tx or eTx
1932-Pin
LVDS Channels
1),
(2)
—
—
—
—
(2)