EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 174

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–2
I/O Standards Support
Stratix IV Device Handbook Volume 1
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This chapter contains the following sections:
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Stratix IV devices support a wide range of industry I/O standards.
I/O standards Stratix IV devices support, as well as the typical applications. These
devices support V
Table 6–1. I/O Standards and Applications for Stratix IV Devices (Part 1 of 2)
3.3-V LVTTL/LVCMOS (1),
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
3.0-V PCI/PCI-X
SSTL-2 Class I and II
SSTL-18 Class I and II
SSTL-15 Class I and II
HSTL-18 Class I and II
HSTL-15 Class I and II
HSTL-12 Class I and II
Differential SSTL-2 Class I and II
Differential SSTL-18 Class I and II
Differential SSTL-15 Class I and II
Differential HSTL-18 Class I and II
Programmable pull-up resistor
Open-drain output
Serial, parallel, and dynamic on-chip termination (OCT)
Differential OCT
Programmable pre-emphasis
Programmable equalization
Programmable differential output voltage (V
“I/O Standards Support”
“I/O Banks” on page 6–5
“I/O Structure” on page 6–17
“On-Chip Termination Support and I/O Termination Schemes” on page 6–24
“OCT Calibration” on page 6–32
“Termination Schemes for I/O Standards” on page 6–38
“Design Considerations” on page 6–46
I/O Standard
CCIO
voltage levels of 3.0, 2.5, 1.8, 1.5, and 1.2 V.
(2)
General purpose
General purpose
General purpose
General purpose
General purpose
DDR SDRAM
DDR2 SDRAM
DDR3 SDRAM
QDRII/RLDRAM II
QDRII/QDRII+/RLDRAM II
General purpose
DDR SDRAM
DDR2 SDRAM
DDR3 SDRAM
Clock interfaces
PC and embedded system
OD
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Chapter 6: I/O Features in Stratix IV Devices
Application
February 2011 Altera Corporation
Table 6–1
I/O Standards Support
lists the