EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 228
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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7–8
Figure 7–3. Number of DQS/DQ Groups per Bank in EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 Devices in the
780-Pin FineLine BGA Package
Notes to
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
(5) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
Stratix IV Device Handbook Volume 1
device, refer to
of the ×4 group are used as R
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Figure
7–3:
“Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page
26 User I/Os
26 User I/Os
32 User I/Os
I/O Bank 2C
I/O Bank 2A
I/O Bank 1C
x16/x18=0
32 User I/Os
x16/x18=0
x16/x18=1
I/O Bank 1A
x16/x18=1
x8/x9=1
x8/x9=1
x8/x9=2
x8/x9=2
DLL0
x4=3
x4=3
x4=4
DLL1
x4=4
UP
and R
(Note
I/O Bank 8A
40 User I/Os
I/O Bank 3A
40 User I/Os
x16/x18=1
x16/x18=1
x8/x9=3
x8/x9=3
DN
x4=6
x4=6
pins for OCT calibration. If two pins of a ×4 group are used as R
1), (2), (3), (4).
24 User I/Os
I/O Bank 8C
x16/x18=0
I/O Bank 3C
24 User I/Os
x8/x9=1
EP4SGX70, EP4SGX110, EP4SGX180, and
x16/x18=0
x4=2
x8/x9=1
x4=2
EP4SGX230 Devices in the
780-Pin FineLine BGA
UP
(5)
and R
24 User I/Os
I/O Bank 7C
24 User I/Os
x16/x18=0
I/O Bank 4C
x16/x18=0
DN
x8/x9=1
x8/x9=1
x4=3
x4=3
pins, but you cannot use a ×4 group for memory interfaces if two pins
Chapter 7: External Memory Interfaces in Stratix IV Devices
40 User I/Os
I/O Bank 7A
I/O Bank 4A
40 User I/Os
x16/x18=1
x16/x18=1
x8/x9=3
x8/x9=3
x4=6
x4=6
UP
7–26.
and R
DLL3
February 2011 Altera Corporation
DLL2
Memory Interfaces Pin Support
DN
pins for OCT calibration, you
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