EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 150

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–34
Stratix IV Device Handbook Volume 1
Programmable Duty Cycle
Programmable Phase Shift
The programmable duty cycle allows PLLs to generate clock outputs with a variable
duty cycle. This feature is supported on the PLL post-scale counters. The duty-cycle
setting is achieved by a low and high time-count setting for the post-scale counters. To
determine duty cycle choices, the Quartus II software uses the frequency input and
the required multiply or divide rate. The post-scale counter value determines the
precision of the duty cycle. Precision is defined as 50% divided by the post-scale
counter value. For example, if the C0 counter is 10, steps of 5% are possible for
duty-cycle choices from 5% to 90%.
If the PLL is in external feedback mode, set the duty cycle for the counter driving the
fbin pin to 50%. Combining the programmable duty cycle with programmable phase
shift allows the generation of precise non-overlapping clocks.
Use phase shift to implement a robust solution for clock delays in Stratix IV devices.
Implement phase shift by using a combination of the VCO phase output and the
counter starting time. A combination of VCO phase output and counter starting time
is the most accurate method of inserting delays because it is only based on counter
settings, which are independent of process, voltage, and temperature (PVT).
You can phase-shift the output clocks from the Stratix IV PLLs in either of these two
resolutions:
■
■
Implement fine-resolution phase shifts by allowing any of the output counters
(C[n..0]) or the m counter to use any of the eight phases of the VCO as the reference
clock. This allows you to adjust the delay time with a fine resolution.
shows the minimum delay time that you can insert using this method.
Equation 5–1. Fine-Resolution Phase Shift
where f
For example, if f
equals 156.25 ps. This phase shift is defined by the PLL operating frequency, which is
governed by the reference clock frequency and the counter settings.
Fine resolution using VCO phase taps
Coarse resolution using counter starting time
R EF
is the input reference clock frequency.
REF
is 100 MHz, N is 1, and M is 8, then f
Φ
fine
=
1
8
T
VCO
=
8f
VCO
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
1
=
8Mf
N
REF
VCO
is 800 MHz and
February 2011 Altera Corporation
PLLs in Stratix IV Devices
Equation 5–1
Φ
fine