EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 339
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
- Current page: 339 of 432
- Download datasheet (11Mb)
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Configuration Features
April 2011 Altera Corporation
Power-On Reset Circuit
V
V
CCPGM
CCPD
1
1
Pins
Pins
The POR circuit keeps the entire system in reset until the power supply voltage levels
have stabilized on power-up. After power-up, the device does not release nSTATUS
until V
On power down, brown-out occurs if the V
below the threshold voltage.
In Stratix IV devices, a pin-selectable option (PORSEL) is provided that allows you to
select between the standard POR time or fast POR time. When PORSEL is driven low,
the standard POR time is 100 ms < T
When PORSEL is driven high, the fast POR time is 4 ms < T
Stratix IV devices have a power supply, V
pins and dual function pins. The supported configuration voltage is 1.8, 2.5, and 3.0 V.
Stratix IV devices do not support 1.5 V configuration.
Use the V
configuration outputs, dedicated configuration bidirectional pins, and some of the
dual functional pins that you use for configuration. With V
input buffers do not have to share power lines with the regular I/O buffer in
Stratix IV devices.
The operating voltage for the configuration input pin is independent of the I/O banks
power supply V
configuration voltage constraints on V
Stratix IV devices have a dedicated programming power supply, V
be connected to 3.0 V/2.5 V to power the I/O pre-drivers and JTAG I/O pins (TCK,
TMS, TDI, TDO, and TRST).
V
when PORSEL is low or 4 ms when PORSEL is high. If these supplies are not ramped up
within this specified time, your Stratix IV device will not configure successfully. If
your system cannot ramp up the power supplies within 100 ms or 4 ms, you must
hold nCONFIG low until all the power supplies are stable.
V
set to 3.0 V, V
2.5 V or lower, V
For more information about configuration pins power supply, refer to
Configuration Pins” on page
CCPGM
CCPD
must be greater than or equal to V
CC
and V
, V
CCPGM
CCAUX
CCPD
CCPD
pin to power all dedicated configuration inputs, dedicated
CCIO
CCPD
, V
must be powered up to 3.0 V. If the V
must ramp up from 0 V to the desired voltage level within 100 ms
CCPT
during configuration. Therefore, Stratix IV devices do not need
must be powered up to 2.5 V.
, V
CCPGM
10–39.
, and V
POR
CCIO
< 300 ms, which has a lower power-ramp rate.
CCPD
CCIO
CCPGM
.
CC
, V
are above the device’s POR trip point.
of the same bank. If V
, for all the dedicated configuration
CCAUX
, V
CCIO
CCPT
POR
CCPGM
Stratix IV Device Handbook Volume 1
of the bank is powered to
, V
< 12 ms.
CCPGM
, the configuration
CCPD
CCIO
, or V
“Device
, which must
of the bank is
CCPD
drops
10–5
Related parts for EP4SGX530HH35C2N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: