EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 335

IC STRATIX IV FPGA 530K 1152HBGA

EP4SGX530HH35C2N

Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

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EP4SGX530HH35C2N
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EP4SGX530HH35C2NAD
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EP4SGX530HH35C2NAE
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© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
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SIV51010-3.3
Overview
Stratix IV Device Handbook Volume 1
April 2011
April 2011
SIV51010-3.3
This chapter describes the configuration, design security, and remote system
upgrades in Stratix
Stratix IV devices provide configuration data decompression. They also provide a
built-in design security feature that protects your designs against IP theft and
tampering of your configuration files.
Stratix IV devices also offer remote system upgrade capability so that you can
upgrade your system in real-time through any network. This helps to deliver feature
enhancements and bug fixes and provides error detection, recovery, and status
information to ensure reliable reconfiguration.
This chapter describes supported configuration schemes for Stratix IV devices,
instructions about how to execute the required configuration schemes, and the
necessary pin settings.
Stratix IV devices use SRAM cells to store configuration data. As SRAM is volatile,
you must download configuration data to the Stratix IV device each time the device
powers up. You can configure Stratix IV devices using one of four configuration
schemes:
All configuration schemes use either an external controller (for example, a MAX
device or microprocessor), a configuration device, or a download cable. For more
information, refer to
This chapter includes the following sections:
Fast passive parallel (FPP)
Fast active serial (AS)
Passive serial (PS)
Joint Test Action Group (JTAG)
“Configuration Schemes” on page 10–2
“Configuration Features” on page 10–4
“Fast Passive Parallel Configuration” on page 10–6
“Fast Active Serial Configuration (Serial Configuration Devices)” on page 10–16
“Passive Serial Configuration” on page 10–24
“JTAG Configuration” on page 10–34
“Device Configuration Pins” on page 10–39
“Configuration Data Decompression” on page 10–47
“Remote System Upgrades” on page 10–49
®
IV devices. To save configuration memory space and time,
“Configuration Features” on page
10. Configuration, Design Security, and
Remote System Upgrades in Stratix IV
10–4.
Devices
Subscribe
®
II

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