EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 411

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 11: SEU Mitigation in Stratix IV Devices
Error Detection Pin Description
Error Detection Pin Description
Table 11–3. CRC_ERROR Pin Description
February 2011 Altera Corporation
CRC_ERROR
Pin Name
Automated Single-Event Upset Detection
CRC_ERROR Pin
f
f
1
1
I/O and
open-drain
Pin Type
After the test completes, Altera recommends reconfiguring the device.
Stratix IV devices offer on-chip circuitry for automated checking of SEU detection.
Some applications that require the device to operate error-free in high-neutron flux
environments require periodic checks to ensure continued data integrity. The error
detection CRC feature ensures data reliability and is one of the best options for
mitigating SEU.
You can implement the error detection CRC feature with existing circuitry in
Stratix IV devices, eliminating the need for external logic. The CRC_ERROR pin reports a
soft error when the configuration CRAM data is corrupted. You must decide whether
to reconfigure the device or to ignore the error.
Depending on the type of error detection feature you choose, you must use different
error detection pins to monitor the data during user mode.
Table 11–3
The WYSIWYG function performs optimization on the Verilog Quartus Mapping
(VQM) netlist within the Quartus II software.
For more information about the stratixiv_crcblock WYSIWYG function, refer to the
AN 539: Test Methodology of Error Detection and Recovery using CRC in Altera FPGA
Devices.
For more information about the CRC_ERROR pin for Stratix IV devices, refer to
Pin-Outs
Active-high signal indicates that the error detection circuit has detected errors in the
configuration CRAM bits. This pin is optional and is used when the error detection CRC
circuit is enabled. When the error detection CRC circuit is disabled, it is a user I/O pin.
To use the CRC_ERROR pin, you can either tie this pin to V
depending on the input voltage specification of the system receiving the signal, you can tie
this pin to a different pull-up voltage.
on the Altera website.
describes the CRC_ERROR pin.
Description
CCPGM
Stratix IV Device Handbook Volume 1
through a 10k Ω resistor or,
Device
11–5