EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 426

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Stratix IV Power Technology
Stratix IV Device Handbook Volume 1
Programmable Power Technology
f
Power consumption also affects thermal management. Stratix IV devices offer a TSD
feature that self-monitors the device junction temperature and can be used with
external circuitry for other activities, such as controlling air flow to the Stratix IV
FPGA.
This chapter contains the following sections:
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■
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The following sections describe Stratix IV programmable power technology.
Stratix IV devices offer the ability to configure portions of the core, called tiles, for
high-speed or low-power mode of operation performed by the Quartus II software
without user intervention. Setting a tile to high-speed or low-power mode is
accomplished with on-chip circuitry and does not require extra power supplies
brought into the Stratix IV device. In a design compilation, the Quartus II software
determines whether a tile must be in high-speed or low-power mode based on the
timing constraints of the design.
For more information about how the Quartus II software uses programmable power
technology when compiling a design, refer to
FPGAs.
A Stratix IV tile can consist of the following:
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■
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All blocks and routing associated with the tile share the same setting of either
high-speed or low-power mode. By default, tiles that include DSP blocks or memory
blocks are set to high-speed mode for optimum performance. Unused DSP blocks and
memory blocks are set to low-power mode to minimize static power. Clock networks
do not support programmable power technology.
With programmable power technology, faster speed grade FPGAs may require less
power because there are fewer high-speed MLAB and LAB pairs, when compared
with slower speed grade FPGAs. The slower speed grade device may have to use
more high-speed MLAB and LAB pairs to meet performance requirements, while the
faster speed grade device can meet performance requirements with MLAB and LAB
pairs in low-power mode.
“Stratix IV Power Technology”
“Stratix IV External Power Supply Requirements”
“Temperature Sensing Diode”
Memory logic array block (MLAB)/logic array block (LAB) pairs with routing to
the pair
MLAB/LAB pairs with routing to the pair and to adjacent digital signal
processing (DSP)/memory block routing
TriMatrix memory blocks
DSP blocks
AN 514: Power Optimization in Stratix IV
Chapter 13: Power Management in Stratix IV Devices
April 2011 Altera Corporation
Stratix IV Power Technology