EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 219

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Stratix IV Devices
Design Considerations
February 2011 Altera Corporation
Non-Voltage-Referenced Standards
Each I/O bank of a Stratix IV device has its own VCCIO pins and supports only one
V
number of input signals with different I/O standard assignments if it meets the V
and V
For output signals, a single I/O bank supports non-voltage-referenced output signals
that are driving at the same voltage as V
V
For example, an I/O bank with a 2.5-V V
inputs and outputs as well as 3.0-V LVCMOS inputs (but not output or bidirectional
pins).
Voltage-Referenced Standards
To accommodate voltage-referenced I/O standards, each Stratix IV device’s I/O bank
supports multiple VREF pins feeding a common V
VREF pins increases as device density increases. If these pins are not used as VREF pins,
they cannot be used as generic I/O pins and must be tied to V
can only have a single V
time.
An I/O bank featuring single-ended or differential standards can support
voltage-referenced standards if all voltage-referenced standards use the same V
setting.
For performance reasons, voltage-referenced input standards use their own V
level as the power source. This feature allows you to place voltage-referenced input
signals in an I/O bank with a V
HSTL-15 input pins in an I/O bank with 2.5-V V
input with parallel OCT enabled requires the V
voltage of the input standard.
Voltage-referenced bidirectional and output signals must be the same as the I/O
bank’s V
bank with a 2.5-V V
Mixing Voltage-Referenced and Non-Voltage-Referenced Standards
An I/O bank can support both voltage-referenced and non-voltage-referenced pins by
applying each of the rule sets individually. For example, an I/O bank can support
SSTL-18 inputs and 1.8-V inputs and outputs with a 1.8-V V
Similarly, an I/O bank can support 1.5-V standards, 1.8-V inputs (but not outputs),
and HSTL and HSTL-15 I/O standards with a 1.5-V V
CCIO
CCIO
, either 1.2, 1.5, 1.8, 2.5, or 3.0 V. An I/O bank can simultaneously support any
CCPD
value, it can only drive out that one value for non-voltage-referenced signals.
CCIO
requirement, as shown in
voltage. For example, you can only place SSTL-2 output pins in an I/O
CCIO
.
CCIO
voltage level and a single V
CCIO
of 2.5 V or below. For example, you can place
Table 6–2 on page
CCIO
CCIO
. Because an I/O bank can only have one
setting can support 2.5-V standard
CCIO
CCIO
REF
. However, the voltage-referenced
of the I/O bank to match the
bus. The number of available
CCIO
6–3.
REF
and 0.75-V V
Stratix IV Device Handbook Volume 1
voltage level at a given
CCIO
CCIO
and a 0.9-V V
or GND. Each bank
REF
.
CCPD
REF
REF
.
CCIO
6–47