EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 82

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–2
Stratix IV DSP Block Overview
Table 4–1. Number of DSP Blocks in Stratix IV Devices (Part 1 of 2)
Stratix IV Device Handbook Volume 1
Stratix IV GX
Stratix IV E
Family
EP4SE230
EP4SE360
EP4SE530
EP4SE820
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX360
EP4SGX530
Device
Each Stratix IV device has two to seven columns of DSP blocks that implement
multiplication, multiply-add, multiply-accumulate (MAC), and dynamic shift
functions efficiently. Architectural highlights of the Stratix IV DSP block include:
■
■
■
■
■
■
■
■
■
■
■
Table 4–1
(1)
(2)
High-performance, power optimized, fully registered, and pipelined
multiplication operations
Natively supported 9-, 12-, 18-, and 36-bit wordlengths
Natively supported 18-bit complex multiplications
Efficiently supported floating-point arithmetic formats (24-bit for single precision
and 53-bit for double precision)
Signed and unsigned input support
Built-in addition, subtraction, and accumulation units to combine multiplication
results efficiently
Cascading 18-bit input bus to form the tap-delay line for filtering applications
Cascading 44-bit output bus to propagate output results from one block to the next
block without external logic support
Rich and flexible arithmetic rounding and saturation units
Efficient barrel shifter support
Loopback capability to support adaptive filtering
161
130
128
120
115
161
104
130
128
128
48
64
lists the number of DSP blocks for the Stratix IV device family.
Multipliers
1,288
1,040
1,024
1,288
1,040
1,024
1,024
9 × 9
960
384
512
920
832
Independent Input and Output Multiplication Operators
Multipliers
12 × 12
966
780
768
720
288
384
690
966
624
780
768
768
Multipliers
18 × 18
644
520
512
480
192
256
460
644
416
520
512
512
Complex
18 × 18
322
260
256
240
128
230
322
208
260
256
256
96
Chapter 4: DSP Blocks in Stratix IV Devices
Multipliers
36 × 36
322
260
256
240
128
230
322
208
260
256
256
96
February 2011 Altera Corporation
Stratix IV DSP Block Overview
High-Precision
Adder Mode
Multipliers
Multiplier
18 × 36
644
520
512
480
192
256
460
644
416
520
512
512
Multipliers
Multiplier
18 × 18
Adder
Mode
1,040
1,024
1,024
1288
1040
1024
1288
Four
960
384
512
920
832