EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 133

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
Figure 5–15. clkena Signals
Note to
(1) You can use the clkena signals to enable or disable the GCLK and RCLK networks or the PLL_<#>_CLKOUT pins.
February 2011 Altera Corporation
output of AND gate
with R2 not bypassed
Figure
output of AND gate
with R2 bypassed
Clock Enable Signals
output of clock
select mux
5–15:
clkena
Figure 5–14
is implemented in Stratix IV devices.
Figure 5–14. clkena Implementation
Notes to
(1) The R1 and R2 bypass paths are not available for the PLL external clock outputs.
(2) The select line is statically controlled by a bit setting in the configuration file (.sof or .pof).
In Stratix IV devices, the clkena signals are supported at the clock network level
instead of at the PLL output counter level. This allows you to gate off the clock even
when you are not using a PLL. You can also use the clkena signals to control the
dedicated external clocks from the PLLs.
a clock output enable. clkena is synchronous to the falling edge of the clock output.
Stratix IV devices also have an additional metastability register that aids in
asynchronous enable and disable of the GCLK and RCLK networks. You can
optionally bypass this register in the Quartus II software.
(Note 1)
Figure
output of clock
select mux
shows how the clock enable and disable circuit of the clock control block
5–14:
clkena
D
(1)
R1
Q
D
R2
(1)
Q
Figure 5–15
(2)
shows a waveform example for
Stratix IV Device Handbook Volume 1
GCLK/
RCLK/
PLL_<#>_CLKOUT (1)
5–17