EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 17

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Overview for the Stratix IV Device Family
Feature Summary
February 2011 Altera Corporation
Stratix IV GX Devices
1
1
Stratix IV GX devices provide up to 48 full-duplex CDR-based transceiver channels
per device:
■
■
The actual number of transceiver channels per device varies with device selection. For
more information about the exact transceiver count in each device, refer to
on page
For more information about transceiver architecture, refer to the
Architecture for Stratix IV Devices
Figure 1–1
Figure 1–1. Stratix IV GX Chip View
Note to
(1) Resource counts vary with device selection, package selection, or both.
Thirty-two out of the 48 transceiver channels have dedicated physical coding
sublayer (PCS) and physical medium attachment (PMA) circuitry and support
data rates between 600 Mbps and 8.5 Gbps
The remaining 16 transceiver channels have dedicated PMA-only circuitry and
support data rates between 600 Mbps and 6.5 Gbps
Figure
1–11.
shows a high-level Stratix IV GX chip view.
1–1:
General Purpose I/O and
PLL
PLL
PLL
PLL
with DPA and Soft CDR
High-Speed LVDS I/O
Transceiver Block
General Purpose
I/O and Memory
General Purpose
I/O and Memory
Interface
Interface
(Note 1)
chapter.
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
FPGA Fabric
PLL
PLL
PLL
PLL
600 Mbps-8.5 Gbps CDR-based Transceiver
General Purpose I/O and 150 Mbps-1.6 Gbps
LVDS interface with DPA and Soft-CDR
General Purpose
I/O and Memory
General Purpose
I/O and Memory
Interface
Interface
Stratix IV Device Handbook Volume 1
PLL
PLL
PLL
PLL
Transceiver
Table 1–1
1–3