EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 343

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Fast Passive Parallel Configuration
April 2011 Altera Corporation
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If you need to stop DCLK, it can only be stopped:
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By stopping DCLK, the configuration circuit allows enough clock cycles to process the
last byte of latched configuration data. When the clock restarts, the MAX II device
must provide data on the DATA[7..0] pins prior to sending the first DCLK rising edge.
If an error occurs during configuration, the device drives its nSTATUS pin low, resetting
itself internally. The low signal on the nSTATUS pin also alerts the MAX II device that
there is an error. If the Auto-restart configuration after error option (available in the
Quartus II software from the General tab of the Device and Pin Options dialog box)
is turned on, the device releases nSTATUS after a reset time-out period (a maximum of
500 μs). After nSTATUS is released and pulled high by a pull-up resistor, the MAX II
device can try to reconfigure the target device without needing to pulse nCONFIG low.
If this option is turned off, the MAX II device must generate a low-to-high transition
(with a low pulse of at least 2 μs) on nCONFIG to restart the configuration process.
If you have enabled the Auto-restart configuration after error option, the nSTATUS pin
transitions from high to low and back again to high when a configuration error is
detected. This appears as a low pulse at the nSTATUS pin with a minimum pulse width
of 10 μs to a maximum pulse width of 500 μs, as defined in the t
The MAX II device can also monitor the CONF_DONE and INIT_DONE pins to ensure
successful configuration. The MAX II device must monitor the CONF_DONE pin to detect
errors and determine when programming completes. If all the configuration data is
sent, but the CONF_DONE or INIT_DONE signals have not gone high, the MAX II device
reconfigures the target device.
If you use the optional CLKUSR pin and nCONFIG is pulled low to restart the
configuration during device initialization, ensure that CLKUSR continues toggling
during the time nSTATUS is low (a maximum of 500 μs).
When the device is in user mode, initiating reconfiguration is done by transitioning
the nCONFIG pin low-to-high. The nCONFIG pin must be low for at least 2 μs. When
nCONFIG is pulled low, the device also pulls nSTATUS and CONF_DONE low and all I/O
pins are tri-stated. After nCONFIG returns to a logic high level and nSTATUS is released
by the device, reconfiguration begins.
three clock cycles after the last data byte was latched into the Stratix IV device
when you use the decompression and/or design security features.
two clock cycles after the last data byte was latched into the Stratix IV device when
you do not use the Stratix IV decompression and/or design security features.
Stratix IV Device Handbook Volume 1
STATUS
specification.
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