EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 32

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–18
Table 1–9. Stratix IV GT Device On-Package Decoupling Information
Stratix IV Device Handbook Volume 1
EP4S40G2F40
EP4S100G2F40
EP4S100G3F45
EP4S100G4F45
EP4S40G5H40
EP4S100G5H40
EP4S100G5F45
Notes to
(1)
(2) For I/O banks 3(*), 4(*), 7(*), and 8(*) only. There is no OPD for I/O bank 1(*), 2(*), 5(*), and 6(*).
Information
Ordering
Table 1–9
devices, contact
Table
refers to production devices on-package decoupling. For more information about decoupling design of engineering sample (ES)
1–9:
Altera Technical
2× 1 uF + 2× 470 nF 10 nF per bank
4× 1 uF + 4× 470 nF 10 nF per bank
Table 1–8
Table 1–8. Stratix IV GT Device Package Options
Table 1–9
Stratix IV GT 40 G Devices
EP4S40G2
EP4S40G5
Stratix IV GT 100 G Devices
EP4S100G2
EP4S100G3
EP4S100G4
EP4S100G5
Notes to
(1) This table represents pin compatability; however, it does not include hard IP block placement compatability.
(2) Devices under the same arrow sign have vertical migration capability.
(3) When migrating between hybrid and flip chip packages, there is an additional keep-out area. For more information,
(4) EP4S40G5 and EP4S100G5 devices with 1517 pin-count are only available in 42.5-mm × 42.5-mm Hybrid flip chip
(5) If you are using the hard IP block, migration is not possible.
V
CC
refer to the
packages.
Support.
Table
lists the resource counts for the Stratix IV GT devices.
lists the Stratix IV GT on-package decoupling information.
Device
1–8:
Altera Device Package Information Data
V
CCIO
(2)
(2)
transceiver block
transceiver block
(40 mm × 40 mm)
100 nF per
100 nF per
H40 (4),
H40 (4),
V
CCL_GXB
1517 Pin
(Note 1)
F40
F40
Sheet.
—
—
(Note
(5)
(5)
Chapter 1: Overview for the Stratix IV Device Family
(3)
1),
V
100 nF
100 nF
(2)
CCA_L/R
February 2011 Altera Corporation
(45 mm × 45 mm)
V
100 nF
100 nF
CCT_L/R
1932 Pin
F45
F45
F45
Architecture Features
—
—
—
V
100 nF
100 nF
CCR_L/R