EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 153

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
February 2011 Altera Corporation
A high-bandwidth PLL provides a fast lock time and tracks jitter on the reference
clock source, passing it through to the PLL output. A low-bandwidth PLL filters out
reference clock jitter but increases lock time. Stratix IV PLLs allow you to control the
bandwidth over a finite range to customize the PLL characteristics for a particular
application. The programmable bandwidth feature in Stratix IV PLLs benefits
applications requiring clock switchover.
A high-bandwidth PLL can benefit a system that must accept a spread-spectrum clock
signal. Stratix IV PLLs can track a spread-spectrum clock by using a high-bandwidth
setting. Using a low-bandwidth setting in this case could cause the PLL to filter out
the jitter on the input clock.
A low-bandwidth PLL can benefit a system using clock switchover. When clock
switchover occurs, the PLL input temporarily stops. A low-bandwidth PLL reacts
more slowly to changes on its input clock and takes longer to drift to a lower
frequency (caused by input stopping) than a high-bandwidth PLL.
Implementation
Traditionally, external components such as the VCO or loop filter control a PLL’s
bandwidth. Most loop filters consist of passive components such as resistors and
capacitors that take up unnecessary board space and increase cost. With Stratix IV
PLLs, all the components are contained within the device to increase performance and
decrease cost.
When you specify the bandwidth setting (low, medium, or high) in the ALTPLL
MegaWizard Plug-in Manager, the Quartus II software automatically sets the
corresponding charge pump and loop filter (Icp, R, C) values to achieve the desired
bandwidth range.
Figure 5–33
Quartus II software. The components are the loop filter resistor, R, the high frequency
capacitor, C
Figure 5–33. Loop Filter Programmable Components
h
shows the loop filter and components that you can set using the
, and the charge pump current, I
PFD
UP
I
I
UP
DN
or I
DN
.
R
C
Stratix IV Device Handbook Volume 1
C
h
5–37