EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 242
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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7–22
Figure 7–17. Number of DQS/DQ Groups per Bank in EP4SE820 Devices in the 1760-pin FineLine BGA Package
Notes to
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
Stratix IV Device Handbook Volume 1
(2), (3),
of the ×4 group are used as R
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Figure
(4)
I/O Bank 1B
36 User I/Os
50 User I/Os
I/O Bank 2B
I/O Bank 1C
I/O Bank 2C
36 User I/Os
I/O Bank 1A
50 User I/Os
I/O Bank 2A
7–17:
50 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
50 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x8/x9=3
x16/x18=1
x32/x36=0
x8/x9=3
x8/x9=3
x8/x9=3
x8/x9=3
x8/x9=3
x4=6
x4=7
DLL1
x4=6
x4=7
DLL0
x4=7
x4=7
I/O Bank 8A
I/O Bank 3A
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
UP
x4=8
x4=8
and R
DN
pins for OCT calibration. If two pins of a ×4 group are used as R
I/O Bank 8B
I/O Bank 3B
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
x4=8
x4=8
I/O Bank 3C
I/O Bank 8C
48 User I/Os
48 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x8/x9=3
in the 1760-Pin FineLine BGA
x8/x9=3
x4=6
x4=6
EP4SE820 Devices
UP
and R
DN
I/O Bank 7C
48 User I/Os
I/O Bank 4C
48 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x8/x9=3
x8/x9=3
pins, but you cannot use a ×4 group for memory interfaces if two pins
x4=6
x4=6
Chapter 7: External Memory Interfaces in Stratix IV Devices
I/O Bank 7B
I/O Bank 4B
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
x4=8
x4=8
I/O Bank 7A
I/O Bank 4A
48 User I/Os
48 User I/Os
x16/x18=2
x32/x36=1
x16/x18=2
x32/x36=1
x8/x9=4
x8/x9=4
UP
x4=8
x4=8
and R
February 2011 Altera Corporation
Memory Interfaces Pin Support
DN
pins for OCT calibration, you
I/O Bank 6C
50 User I/Os
50 User I/Os
I/O Bank 5C
36 User I/Os
x16/x18=1
x32/x36=0
I/O Bank 5A
50 User I/Os
I/O Bank 6B
36 User I/Os
I/O Bank 5B
I/O Bank 6A
x16/x18=1
x32/x36=0
50 User I/Os
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x16/x18=1
x32/x36=0
x8/x9=3
x16/x18=1
x32/x36=0
x8/x9=3
x8/x9=3
x8/x9=3
x8/x9=3
x8/x9=3
x4=7
x4=7
x4=6
x4=7
DLL2
x4=6
DLL3
x4=7
(Note
1),
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