EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 67

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
Table 3–5. M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2)
Table 3–6. M144K Block Mixed-Width Configurations (Simple Dual-Port Mode)
February 2011 Altera Corporation
1K × 8
512 × 16
256 × 32
1K × 9
512 × 18
256 × 36
16K × 8
8K × 16
4K × 32
2K × 64
16K × 9
8K × 18
4K × 36
2K × 72
Read Port
Read Port
Table 3–6
mode.
In simple dual-port mode, M9K and M144K blocks support separate write-enable and
read-enable signals. You can save power by keeping the read-enable signal low
(inactive) when not reading. Read-during-write operations to the same address can
either output a “don’t care” value or “old data” value. To choose the desired behavior,
set the read-during-write behavior to either don’t care or old data in the RAM
MegaWizard Plug-In Manager in the Quartus II software. For more information, refer
to
MLABs only support a write-enable signal. For MLABs, you can set the same-port
read-during-write behavior to don’t care and the mixed-port read-during-write
behavior to either don’t care or old data. The available choices depend on the
configuration of the MLAB. There is no “new data” option for MLABs.
8K × 1
v
v
v
16K × 8
—
—
—
“Read-During-Write Behavior” on page
v
v
v
v
—
—
—
—
4K × 2
lists the mixed-width configurations for M144K blocks in simple dual-port
v
v
v
—
—
—
8K × 16
v
v
v
v
—
—
—
—
2K × 4
v
v
v
—
—
—
4K × 32
v
v
v
v
—
—
—
—
1K × 8
v
v
v
—
—
—
2K × 64
512 × 16
v
v
v
v
—
—
—
—
Write Port
v
v
v
—
—
—
Write Port
3–18.
16K × 9
256 × 32
v
v
v
v
—
—
—
—
v
v
v
—
—
—
8K × 18
1K × 9
v
v
v
v
—
—
—
—
—
—
—
v
v
v
Stratix IV Device Handbook Volume 1
512 × 18
4K × 36
—
—
—
v
v
v
—
—
—
—
v
v
v
v
256 × 36
2K × 72
—
—
—
v
v
v
—
—
—
—
v
v
v
v
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