EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 379

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Device Configuration Pins
Table 10–10. Dedicated Configuration Pins on the Stratix IV Device (Part 4 of 4)
April 2011 Altera Corporation
nCSO
DCLK
DATA0
DATA[7..1]
Pin Name
User Mode
FPP mode.
mode. I/O
N/A in AS
in PS or
N/A
N/A
I/O
Configuration
(PS, FPP, AS)
Synchronous
configuration
configuration
PS, FPP, AS
schemes
schemes
Scheme
Parallel
(FPP)
AS
Output (AS)
(PS, FPP)
Pin Type
Output
Inputs
Input
Input
Output control signal from the Stratix IV device to the serial
configuration device in AS mode that enables the
configuration device.
In AS mode, nCSO has an internal pull-up resistor that is
always active.
In PS and FPP configurations, DCLK is the clock input used
to clock data from an external source into the target device.
Data is latched into the device on the rising edge of DCLK.
In AS mode, DCLK is an output from the Stratix IV device
that provides timing for the configuration interface. In AS
mode, DCLK has an internal pull-up resistor (typically
25 kΩ) that is always active.
In AS configuration schemes, this pin is driven into an
inactive state after configuration completes. You can use
this pin as a user I/O during user mode.
In PS or FPP schemes that use a control host, you must
drive DCLK either high or low, whichever is more
convenient. In passive schemes, you cannot use DCLK as a
user I/O during user mode.
Toggling this pin after configuration does not affect the
configured device.
Data input. In serial configuration modes, bit-wide
configuration data is presented to the target device on the
DATA0 pin.
In AS mode, DATA0 has an internal pull-up resistor that is
always active.
After PS or FPP configuration, DATA0 is available as a user
I/O pin. The state of this pin depends on the Dual-Purpose
Pin settings.
Data inputs. Byte-wide configuration data is presented to
the target device on DATA[7..0].
In serial configuration schemes, they function as user I/O
pins during configuration, which means they are tri-stated.
After FPP configuration, DATA[7..1] are available as user
I/O pins. The state of these pins depends on the
Dual-Purpose Pin settings.
Description
Stratix IV Device Handbook Volume 1
10–45