EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 392

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

10–58
Table 10–14. Remote System Upgrade Registers
Stratix IV Device Handbook Volume 1
Shift register
Control register
Update register
Status register
Register
Remote System Upgrade Registers
This register is accessible by the logic array and allows the update, status, and control registers to be
written and sampled by user logic.
This register contains the current page address, user watchdog timer settings, and one bit specifying
whether the current configuration is a factory configuration or an application configuration. During a read
operation in an application configuration, this register is read into the shift register. When a
reconfiguration cycle is initiated, the contents of the update register are written into the control register.
This register contains data similar to that in the control register. However, it can only be updated by the
factory configuration by shifting data into the shift register and issuing an update operation. When a
reconfiguration cycle is triggered by the factory configuration, the control register is updated with the
contents of the update register. During a capture in a factory configuration, this register is read into the
shift register.
This register is written to by the remote system upgrade circuitry on every reconfiguration to record the
cause of the reconfiguration. This information is used by the factory configuration to determine the
appropriate action following a reconfiguration. During a capture cycle, this register is read into the shift
register.
The remote system upgrade block contains a series of registers that store the page
addresses, watchdog timer settings, and status information.
registers.
The remote system upgrade control and status registers are clocked by the 10-MHz
internal oscillator (the same oscillator that controls the user watchdog timer).
However, the remote system upgrade shift and update registers are clocked by the
user clock input (RU_CLK).
Remote System Upgrade Control Register
The remote system upgrade control register stores the application configuration page
address and user watchdog timer settings. The control register functionality depends
on the remote system upgrade mode selection. In remote update mode, the control
register page address bits are set to all zeros (24'b0 = 0×000000) at power up to load
the factory configuration. A factory configuration in remote update mode has write
access to this register.
Figure 10–26
the numbers show the bit position of a setting within a register. For example, bit
number 25 is the enable bit for the watchdog timer.
Figure 10–26. Remote System Upgrade Control Register
37 36 35 34 33 32 31 30 29 28 27 26
and
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Table 10–15
Wd_timer[11..0]
specify the control register bit positions. In the figure,
Description
Wd_en
25
24 23 22 .. 3
Dedicated Remote System Upgrade Circuitry
PGM[23..0]
Table 10–14
April 2011 Altera Corporation
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