EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 344

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

10–10
Figure 10–2. Multi-Device FPP Configuration Using an External Host
Note to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Stratix IV devices in the chain. V
Stratix IV Device Handbook Volume 1
to meet the V
I/Os with V
Figure
(MAX II Device or
Microprocessor)
External Host
ADDR DATA[7..0]
CCPGM.
10–2:
Memory
IH
specification of the I/O standard on the device and the external host. Altera recommends powering up all configuration system
Figure 10–2
device. This circuit is similar to the FPP configuration circuit for a single device,
except the devices are cascaded for multi-device configuration.
In a multi-device FPP configuration, the first device’s nCE pin is connected to GND
while its nCEO pin is connected to nCE of the next device in the chain. The last device’s
nCE input comes from the previous device, while its nCEO pin is left floating. After the
first device completes configuration in a multi-device configuration chain, its nCEO pin
drives low to activate the second device’s nCE pin, which prompts the second device
to begin configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent to the
MAX II device. All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and
CONF_DONE) are connected to every device in the chain. The configuration signals may
require buffering to ensure signal integrity and prevent clock skew problems. Ensure
that the DCLK and DATA lines are buffered for every fourth device. Because all device
CONF_DONE pins are tied together, all devices initialize and enter user mode at the same
time.
All nSTATUS and CONF_DONE pins are tied together; if any device detects an error,
configuration stops for the entire chain and you must reconfigure the entire chain. For
example, if the first device flags an error on nSTATUS, it resets the chain by pulling its
nSTATUS pin low. This behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the devices release
their nSTATUS pins after a reset time-out period (a maximum of 500 μs). After all
nSTATUS pins are released and pulled high, the MAX II device tries to reconfigure the
chain without pulsing nCONFIG low. If this option is turned off, the MAX II device
must generate a low-to-high transition (with a low pulse of at least 2 μs) on nCONFIG to
restart the configuration process.
V
10 kΩ
CCPGM
(1)
shows how to configure multiple Stratix IV devices using a MAX II
V
CCPGM
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
10 kΩ
GND
(1)
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
Stratix IV Device 1
MSEL[2..0]
nCEO
GND
CONF_DONE
nSTATUS
nCE
nCONFIG
DCLK
DATA[7..0]
Stratix IV Device 2
Fast Passive Parallel Configuration
April 2011 Altera Corporation
CCPGM
MSEL[2..0]
must be high enough
nCEO
GND
N.C.