EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 127

EP4SGX530HH35C2N

Manufacturer Part Number

EP4SGX530HH35C2N

Description

IC STRATIX IV FPGA 530K 1152HBGA

Manufacturer

Altera

Series

Stratix® IV GXr

Datasheets

1.EP4SGX110DF29C3N.pdf (80 pages)

2.EP4SGX110DF29C3N.pdf (1154 pages)

3.EP4SGX110DF29C3N.pdf (432 pages)

4.EP4SGX110DF29C3N.pdf (22 pages)

5.EP4SGX110DF29C3N.pdf (30 pages)

6.EP4SGX110DF29C3N.pdf (72 pages)

7.EP4SGX530HH35C2N.pdf (1145 pages)

Specifications of EP4SGX530HH35C2N

Number Of Logic Elements/cells

531200

Number Of Labs/clbs

21248

Total Ram Bits

27376

Number Of I /o

564

Voltage - Supply

0.87 V ~ 0.93 V

Mounting Type

Surface Mount

Operating Temperature

0°C ~ 85°C

Package / Case

1152-HBGA

Family Name

Stratix® IV

Number Of Logic Blocks/elements

531200

# Registers

424960

# I/os (max)

560

Process Technology

40nm

Operating Supply Voltage (typ)

900mV

Logic Cells

531200

Ram Bits

28033024

Operating Supply Voltage (min)

0.87V

Operating Supply Voltage (max)

0.93V

Operating Temp Range

0C to 85C

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

1152

Package Type

FCHBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Number Of Gates

Lead Free Status / Rohs Status

Compliant

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Quantity

Price

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Part Number:

EP4SGX530HH35C2N

Manufacturer:

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Quantity:

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Company:

BOSTOCK HK LIMITED

Part Number:

EP4SGX530HH35C2N

Manufacturer:

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Company:

BOSTOCK HK LIMITED

Part Number:

EP4SGX530HH35C2NAD

Manufacturer:

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Company:

BOSTOCK HK LIMITED

Part Number:

EP4SGX530HH35C2NAE

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Chapter 5: Clock Networks and PLLs in Stratix IV Devices

Clock Networks in Stratix IV Devices

Table 5–2. Clock Input Pin Connectivity to the GCLK Networks

Table 5–3. Clock Input Pin Connectivity to the RCLK Networks (Part 1 of 2)

February 2011 Altera Corporation

GCLK0

GCLK1

GCLK2

GCLK3

GCLK4

GCLK5

GCLK6

GCLK7

GCLK8

GCLK9

GCLK10

GCLK11

GCLK12

GCLK13

GCLK14

GCLK15

RCLK [0, 4, 6, 10]

RCLK [1, 5, 7, 11]

RCLK [2, 8]

RCLK [3, 9]

RCLK [13, 17, 21, 23,

27, 31]

RCLK [12, 16, 20, 22,

26, 30]

RCLK [15, 19, 25, 29]

RCLK [14, 18, 24, 28]

RCLK [35, 41]

Clock Resources

Clock Resource

PLL Clock Outputs

Stratix IV PLLs can drive both GCLK and RCLK networks, as described in

on page 5–13

Table 5–2

Table 5–3

Stratix IV devices. A given clock input pin can drive two adjacent RCLK networks to

create a dual-regional clock network.

—

lists the connection between the dedicated clock input pins and GCLKs.

lists the connectivity between the dedicated clock input pins and RCLKs in

—

and

—

v —

Table 5–6 on page

—

v —

—

CLK (p/n Pins)

5–13.

—

CLK (p/n Pins)

—

Stratix IV Device Handbook Volume 1

—

Table 5–5

—

5–11

—

EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 127

EP4SGX530HH35C2N

Specifications of EP4SGX530HH35C2N

Available stocks

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