EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 318

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–40
Stratix IV Device Handbook Volume 1
Using Both Center Left and Right PLLs
You can use both center left and right PLLs to drive DPA-enabled channels
simultaneously, as long as they drive these channels in their adjacent banks only, as
shown in
If one of the center left and right PLLs drives the top and bottom banks, you cannot
use the other center left and right PLL to drive differential channels, as shown in
Figure
If the top PLL_L2 and PLL_R2 drives DPA-enabled channels in the lower differential
bank, the PLL_L3 and PLL_R3 cannot drive DPA-enabled channels in the upper
differential banks and vice versa. In other words, the center left and right PLLs cannot
drive cross-banks simultaneously, as shown in
Figure 8–32. Center Left and Right PLLs Driving DPA-Enabled Differential I/Os
8–32.
Figure
(PLL_L2/PLL_R2)
(PLL_L3/PLL_R3)
Left/Right PLL
Left/Right PLL
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
Reference
Reference
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Center
Center
8–32.
CLK
CLK
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Figure
8–33.
Differential Pin Placement Guidelines
(PLL_L3/PLL_R3)
(PLL_L2/PLL_R2)
February 2011 Altera Corporation
Left/Right PLL
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
Reference
Left/Right PLL
DPA-enabled
DPA-enabled
DPA-enabled
Reference
CLK
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Center
Center
CLK
Unused
PLL