EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 121

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Clock Networks in Stratix IV Devices
Figure 5–3. RCLK Networks (EP4S40G2, EP4S100G2, EP4SGX180, and EP4SGX230 Devices)
Note to
(1) A maximum of four signals from the core can drive into each group of RCLKs. For example, only four core signals can drive into RCLK[0..5] and
Figure 5–4. RCLK Networks (EP4S40G5, EP4S100G3, EP4S100G4, EP4S100G5, EP4SE360, EP4SE530, EP4SE820,
EP4SGX290, EP4SGX360, and EP4SGX530 Devices)
Notes to
(1) The corner RCLK[64..87] can only be fed by their respective corner PLL outputs. For more information about connectivity, refer to
(2) The EP4S40G5 and EP4SE360 devices have up to eight PLLs. For more information about PLL availability, refer to
(3) A maximum of four signals from the core can drive into each group of RCLKs. For example, only four core signals can drive into RCLK[0..5] and
February 2011 Altera Corporation
another four core signals can drive into RCLK[54..63] at any one time.
page
another four core signals can drive into RCLK[54..63] at any one time.
Figure
Figure
5–13.
5–3:
5–4:
CLK[0..3]
CLK[0..3]
L2
L3
L1
L2
L3
L4
RCLK[82..87]
RCLK[64..69]
RCLK[6..11]
RCLK[0..5]
RCLK[0..5]
RCLK[6..11]
RCLK[12..21] RCLK[22..31]
RCLK[54..63] RCLK[44..53]
RCLK[54..63] RCLK[44..53]
RCLK[12..21] RCLK[22..31]
(Note
CLK[12..15]
CLK[12..15]
CLK[4..7]
Q1
Q4
CLK[4..7]
Q1 Q2
Q4 Q3
T1
B1
T1
B1
1), (2),
T2
B2
T2
B2
Q2
Q3
(3)
RCLK[38..43]
RCLK[32..37]
RCLK[76..81]
RCLK[32..37]
RCLK[70..75]
RCLK[38..43]
R2
R3
R1
R2
R3
R4
CLK[8..11]
CLK[8..11]
Stratix IV Device Handbook Volume 1
(Note 1)
Table 5–7 on page
Table 5–6 on
5–19.
5–5