EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 151

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Figure 5–31. Delay Insertion Using VCO Phase Output and Counter Delay Time
February 2011 Altera Corporation
CLK0
CLK1
CLK2
135
180
225
270
315
45
90
0
1/8 t
VCO
Equation 5–2
the start of the counters for a predetermined number of counter clocks.
Equation 5–2. Coarse-Resolution Phase Shift
where C is the count value set for the counter delay time (this is the initial setting in
the “PLL usage” section of the compilation report in the Quartus II software). If the
initial value is 1, C – 1 = 0° phase shift.
Figure 5–31
VCO phase-taps method. The eight phases from the VCO are shown and labeled for
reference. For this example, CLK0 is based on the 0phase from the VCO and has the C
value for the counter set to one. The CLK1 signal is divided by four, two VCO clocks
for high time and two VCO clocks for low time. CLK1 is based on the 135° phase tap
from the VCO and also has the C value for the counter set to one. In this case, the two
clocks are offset by 3
C value for the counter set to three. This arrangement creates a delay of 2
(two complete VCO periods).
You can use coarse- and fine-phase shifts to implement clock delays in Stratix IV
devices.
Stratix IV devices support dynamic phase-shifting of VCO phase taps only. You can
reconfigure the phase shift any number of times. Each phase shift takes about one
SCANCLK cycle, allowing you to implement large phase shifts quickly.
t
d0-1
t
d0-2
shows an example of phase-shift insertion with fine resolution using the
shows the coarse-resolution phase shifts are implemented by delaying
t
VCO
Φ
FINE
. CLK2 is based on the 0phase from the VCO but has the
Φ
coarse
=
C − 1
f
V
co
=
(C − 1)N
Mf
REF
Stratix IV Device Handbook Volume 1
Φ
COARSE
5–35