EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 21
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Chapter 1: Overview for the Stratix IV Device Family
Document Revision History
Table 1–10. Document Revision History (Part 2 of 2)
February 2011 Altera Corporation
June 2009
April 2009
March 2009
March 2009
November 2008
July 2008
May 2008
Date
Version
2.0
2.4
2.3
2.2
2.1
1.1
1.0
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Revised “Introduction”.
Initial release.
Updated Table 1–1.
Minor text edits.
Added Table 1–5, Table 1–6, and Figure 1–3.
Updated Figure 1–5.
Updated Table 1–1, Table 1–2, Table 1–3, and Table 1–4.
Updated “Introduction”, “Feature Summary”, “Stratix IV GX Devices”, “Stratix IV GT
Devices”, “Architecture Features”, and “FPGA Fabric and I/O Features”
Updated “Feature Summary”, “Stratix IV GX Devices”, “Stratix IV E Device”, “Stratix IV
GT Devices”, “Signal Integrity”
Removed Tables 1-5 and 1-6
Updated Figure 1–4
Updated “Introduction”, “Feature Summary”, “Stratix IV Device Diagnostic Features”,
“Signal Integrity”, “Clock Networks”,“High-Speed Differential I/O with DPA and Soft-
CDR”, “System Integration”, and “Ordering Information” sections.
Added “Stratix IV GT 100G Devices” and “Stratix IV GT 100G Transceiver Bandwidth”
sections.
Updated Table 1–1, Table 1–2, Table 1–3, and Table 1–4.
Added Table 1–5 and Table 1–6.
Updated Figure 1–3 and Figure 1–4.
Added Figure 1–5.
Removed “Referenced Documents” section.
Updated “Feature Summary” on page 1–1.
Updated “Stratix IV Device Diagnostic Features” on page 1–7.
Updated “FPGA Fabric and I/O Features” on page 1–8.
Updated Table 1–1.
Updated Table 1–2.
Updated “Table 1–5 shows the total number of transceivers available in the Stratix IV GT
Device.” on page 1–15.
Changes
Stratix IV Device Handbook Volume 1
1–21