XC5VSX50T-2FF665C Xilinx Inc, XC5VSX50T-2FF665C Datasheet - Page 151

• Manufacturer Part Number: XC5VSX50T-2FF665C
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-2FF665C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Case 1: Writing to an Empty FIFO
Prior to the operations performed in
X-Ref Target - Figure 4-21
Clock Event 1 and Clock Event 3: Write Operation and Deassertion of EMPTY
Signal
During a write operation to an empty FIFO, the content of the FIFO at the first address is
replaced by the data value on the DI pins. Three read-clock cycles later (four read-clock
cycles for FWFT mode), the EMPTY pin is deasserted when the FIFO is no longer empty.
The RDCOUNT also increments by one due to an internal read preloading the data to the
output registers.
For the example in
event 1 is with respect to the write-clock, while clock event 3 is with respect to the read-
clock. Clock event 3 appears four read-clock cycles after clock event 1.
•
•
•
•
If the rising WRCLK edge is close to the rising RDCLK edge, EMPTY could be deasserted
one RDCLK period later.
AEMPTY
WRCLK
EMPTY
RDCLK
WREN
RDEN
At time T
inputs of the FIFO.
At time T
the WREN input of the FIFO.
At time T
output pins of the FIFO. In standard mode, data 00 does not appear at the DO output
pins of the FIFO.
At time T
mode, EMPTY is deasserted one read-clock earlier than clock event 3.
DO
DI
FDCK_DI
FCCK_WREN
FCKO_DO
FCKO_EMPTY
Figure 4-21: Writing to an Empty FIFO in FWFT Mode
Figure
, before clock event 1 (WRCLK), data 00 becomes valid at the DI
, after clock event 3 (RDCLK), data 00 becomes valid at the DO
1
00
, before clock event 1 (WRCLK), write enable becomes valid at
, after clock event 3 (RDCLK), EMPTY is deasserted. In standard
www.xilinx.com
4-21, the timing diagram is drawn to reflect FWFT mode. Clock
T
T
FCCK_WREN
FDCK_DI
01
Figure
4-21, the FIFO is completely empty.
02
FIFO Timing Models and Parameters
2 3
03
T
T
FDCK_DI
FCKO_AEMPTY
00
T
04
FCKO_EMPTY
T
FCKO_DO
05
4
ug190_4_18_032506
06
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