XC5VSX50T-2FF665C Xilinx Inc, XC5VSX50T-2FF665C Datasheet - Page 295

• Manufacturer Part Number: XC5VSX50T-2FF665C
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-2FF665C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Transmitter Termination
Receiver Termination
The Virtex-5 FPGA LVDS transmitter does not require any external termination.
lists the allowed attributes corresponding to the Virtex-5 FPGA LVDS current-mode
drivers. Virtex-5 FPGA LVDS current-mode drivers are a true current source and produce
the proper (EIA/TIA compliant) LVDS signal.
Figure 6-87
50 Ω transmission lines.
X-Ref Target - Figure 6-87
Figure 6-88
50 Ω transmission lines.
X-Ref Target - Figure 6-88
Table 6-36
Table 6-36: Allowed Attributes of the LVDS I/O Standard
IOSTANDARD
DIFF_TERM
Attributes
LVDS_25
External Termination
lists the available Virtex-5 FPGA LVDS I/O standards and attributes supported.
is an example of a differential termination for an LVDS receiver on a board with
is an example of differential termination for an LVDS receiver on a board with
Figure 6-88: LVDS_25 With DIFF_TERM Receiver Termination
LVDS_25
IOB
Figure 6-87: LVDS_25 Receiver Termination
www.xilinx.com
IOB
IBUFDS/IBUFGDS
0
TRUE, FALSE
Z
Z
0
0
R DIFF = 2Z 0 = 100Ω
= 50Ω
= 50Ω
Specific Guidelines for I/O Supported Standards
0
Z 0
Z 0
LVDS_25, LVDSEXT_25
Primitives
IOB
R DIFF = 100Ω
IOB
OBUFDS/OBUFTDS
+
–
N/A
LVDS_25
LVDS_25
+
–
ug190_6_81_030506
ug190_6_82_030506
Data in
Table 6-36
295