XC5VSX50T-2FF665C Xilinx Inc, XC5VSX50T-2FF665C Datasheet - Page 374

• Manufacturer Part Number: XC5VSX50T-2FF665C
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-2FF665C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 8: Advanced SelectIO Logic Resources
Table 8-7: OSERDES Attribute Summary
374
OSERDES Attribute
DATA_RATE_OQ
DATA_RATE_TQ
DATA_WIDTH
SERDES_MODE
TRISTATE_WIDTH
OSERDES Attributes
DATA_RATE_OQ Attribute
DATA_RATE_TQ Attribute
Defines whether data (OQ) changes at every
clock edge or every positive clock edge with
respect to CLK.
Defines whether the 3-state (TQ) changes at
every clock edge, every positive clock edge
with respect to clock, or is set to buffer
configuration.
Defines the parallel-to-serial data converter
width. This value also depends on the
DATA_RATE_OQ value.
Defines whether the OSERDES module is a
master or slave when using width expansion.
Defines the parallel to serial 3-state converter
width.
Table 8-7
primitive. The table includes the default values.
The DATA_RATE_OQ attribute defines whether data is processed as single data rate (SDR)
or double data rate (DDR). The allowed values for this attribute are SDR and DDR. The
default value is DDR.
The DATA_RATE_TQ attribute defines whether 3-state control is to be processed as single
data rate (SDR) or double data rate (DDR). The allowed values for this attribute are SDR
and DDR. The default value is DDR.
lists and describes the various attributes that are available for the OSERDES
Description
www.xilinx.com
String: SDR or DDR
String: BUF, SDR, or DDR
Integer: 2, 3, 4, 5, 6, 7, 8, or 10.
If DATA_RATE_OQ = DDR,
value is limited to 4, 6, 8, or 10.
If DATA_RATE_OQ = SDR,
value is limited to
2, 3, 4, 5, 6, 7, or 8.
String: MASTER or SLAVE
Integer: 1 or 4
If DATA_RATE_TQ = DDR,
DATA_WIDTH = 4, and
DATA_RATE_OQ = DDR,
value is limited to 4.
For all other settings of
DATA_RATE_TQ,
DATA_WIDTH, and
DATA_RATE_OQ, value is
limited to 1.
Value
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Default Value
DDR
DDR
4
MASTER
4