MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 266

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MC68030FE25C

Manufacturer Part Number
MC68030FE25C
Description
IC MPU 32BIT ENHANCED 132-CQFP
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68030FE25C

Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
CQUAD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68030FE25C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68030FE25C
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
MOTOROLA
osc, LEs
PLUS 5
VOLTS
RESET -- !
for a reset operation is described in 8.1.1 Reset Exception.
When a reset instruction is executed, the processor drives the RESET signal
for 512 clock cycles. In this case, the processor resets the external devices
of the system, and the internal registers of the processor are unaffected. The
external devices connected to the RESET signal are reset at the completion
of the reset instruction. An external RESET signal that is asserted to the
processor during execution of a reset instruction must extend beyond the
reset period of the instruction by at least eight clock cycles to reset the
processor. Figure 7-65 shows the timing information for the reset instruction.
Resetting the processor causes any bus cycle in progress to terminate as if
DSACKx, BERR, or STERM had been asserted. In addition, the processor
initializes registers appropriately for a reset exception. Exception processing
VCC
CLK
Figure 7-64. Initial Reset Operation Timing
MC68030 USER'S MANUAL
I ~
~'<4CLOOKS 4
BUS STATE UNKNOWN
t = >520 C I O C K S ~ I ~
HI6H IMPEDANCE READ MODE, ADDRESS pl~ READ
ENTIRE BUS
' ~
NEGATED, DATA BUS IN |
A L ONTROLS,ONA S
BUS DR VEN
/
- - STARTS
7-105
ISP
7

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