MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 441

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

10
An - 2 *LENGTH = FINAL An
10-54
them to the operand CIR.
the operands are read from memory with ascending addresses also, and the
transferred. The MC68030 transfers the data using long-word transfers when-
effective address specified in the instruction using long-word transfers when-
ever possible. If DR=0, the main processor reads the number of operands
specified in the register select mask from the effective address and writes
address register used is incremented by the size of an operand after each
operand is transferred. The address register used with the (An) + addressing
with descending addresses, but the bytes within each operand are written
to memory with ascending addresses. As an example, Figure 10-38 shows
the format in long-word-oriented memory for two 12-byte operands trans-
ferred from the coprocessor to the effective address using the -(An) ad-
the address register has been decremented by the total number of bytes
ever possible.
if DR = 1, the main processor reads the number of operands specified in the
register select mask from the operand CIR and writes these operands to the
For the control addressing modes, the operands are transferred to or from
memory using ascending addresses. For the postincrement addressing mode,
mode is incremented by the total number of bytes transferred during the
primitive execution.
For the predecrement addressing mode, the operands are written to memory
dressing mode: The processor decrements the address register by the size
of an operand before the operand is transferred. It writes the bytes of the
operand to ascending memory addresses. When the transfer is complete,
An - LENGTH-~I=~
INITIAL An
Figure 10-38. Operand Format in Memory for TranSfer to - ( A n )
31
OP1. BYTE (0)
0P0. BYTE (0)
NOTE:
MC68030 USER'S MANUAL
oPo, Byte (0) is the first byte written to memory
OP1, Byte (0) is the first byte of the second operand written to memory
OP1, Byte (L-l) is the last byte written to memory
OPO, Byte (L-1) is the last byte of the first operand written to memory
23
15
7
OP1, BYTE (L-l)
OPO, BYTE (L-l)
MOTOROLA
0