MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 420

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
10.3.10 Instruction Address CIR
10.3.11 Operand Address CIR
10.4 COPROCESSOR RESPONSE PRIMITIVES
When the coprocessor requests the address of the instruction it is currently
When a coprocessor requests an operand address transfer between the main
The response primitives are primitive instructions that the coprocessor issues
to the main processor during the execution of a coprocessor instruction. The
command word written to the command CIR or a condition selector in the
violation exception processing (refer to 10.5.2.1 PROTOCOL VIOLATIONS).
This processing of undefined primitives supports emulation of extensions to
the M68000 coprocessor response primitive set by the protocol violation
executing, the main processor transfers this address to the 32-bit instruction
address CIR. Any transfer of the scanPC is also performed through the in-
struction address CIR (refer to 10.4.17 Transfer Status Register and ScanPC
Primitive). The offset from the base address of the CIR set for the instruction
address CIR is $18.
processor and the coprocessor, the address is transferred through the 32-bit
operand address CIR. The offset from the base address of the CIR set for the
operand address CIR is $1C.
coprocessor uses response primitives to communicate status information
and service requests to the main processor. In response to an instruction
condition CIR, the coprocessor returns a response primitive in the response
CIR. Within the general and conditional instruction categories, individual
instructions are distinguished by the operation of the coprocessor hardware
and also by services specified by coprocessor response primitives provided
by the main processor.
Subsequent paragraphs, beginning with 10.4.2 Coprocessor Response Pri-
mitive General Format, consist of detailed descriptions of the M68000 co-
processor response primitives supported by the MC68030. Any response
primitive that the MC68030 does not recognize causes it to initiate protocol
exception handler. Exception processing related to the coprocessor interface
is discussed in 10.5 EXCEPTIONS.
MC68030 USER'S MANUAL
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