MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 144

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Floating-Point Unit
6.6.2.2 TRAP ENABLED RESULTS (FPCR SNAN BIT SET). If the destination is not a
floating-point data register (FMOVE OUT instruction), the destination (memory or integer
data register) is written with the same data as though the trap were disabled (FPCR SNAN
bit clear), and then control is passed to the user SNAN handler as a post-instruction excep-
tion. If desired, the user SNAN handler can overwrite the result.
For floating-point data register destinations, the source (if register-to-register instruction)
and destination floating-point data registers are not modified. Control is passed to the user
SNAN handler as a pre-instruction exception when the next floating-point instruction is
encountered. In this case, the SNAN user handler should supply the result.
The SNAN user handler must execute an FSAVE instruction as the first floating-point
instruction to prevent the FPU from taking more exceptions. The FSAVE frame generates a
floating-point frame that contains the source operand that has been converted to extended
precision. If the destination is a floating-point data register, it contains the original value. The
FPIAR points to the floating-point instruction that caused the exception. In addition, if the
offending instruction is FMOVE OUT, an integer stack frame format $3 is created as a result
of a post-instruction exception, the effective address of the destination memory operand is
provided. The effective address field is undefined if the destination is an integer data regis-
ter.
The user SNAN exception handler may discard the floating-point state frame once the han-
dler has completed. The RTE instruction must be executed to return to normal instruction
flow.
6.6.3 Operand Error
The operand error exception encompasses problems arising in a variety of operations,
including those errors not frequent or important enough to merit a specific exceptional con-
dition. Basically, an operand error occurs when an operation has no mathematical interpre-
tation for the given operands. Table 6-12 lists the possible operand errors, both native and
non-native to the MC68060, which the M68060SP unimplemented instruction exception
handler can report. When an operand error occurs, the OPERR bit is set in the FPSR EXC
byte.
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M68060 USER’S MANUAL
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