MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 211

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Bus Operation
The MC68060 can be in any one of seven bus arbitration states during bus operation: reset,
AM-implicit own, AM-explicit own, snoop, implicit ownership, explicit ownership, and the end
tenure states.
The reset state is entered whenever RSTI is asserted in any bus arbitration state, except the
explicit ownership state. For that state, the end tenure state is entered prior to entering the
reset state.This is done to ensure other bus masters are capable of taking the bus away from
the processor when it is reset. When RSTI is negated, the processor proceeds to the implicit
ownership state or alternate master implicit ownership state, depending on BG. If an alter-
nate master asserts TS or has asserted TS in the past, the processor waits for BTT to assert
(or alternatively, for BB to go from being asserted to being negated) before taking the bus,
even though BG may be asserted to the processor.
The AM-implicit own state denotes the MC68060 does not have ownership (BG negated) of
the bus and is not in the process of snooping an access, and the alternate has not begun its
tenure by asserting TS (alternate master TS or SNOOP negated). In the AM-implicit own
state, the MC68060 does not drive the bus. The processor enters the AM-explicit own state
when TS is asserted by the alternate master. Once in the AM-explicit own state, the proces-
sor waits for the alternate master to transition and negate BB (or alternatively assert BTT)
before recognizing that a change of tenure has occurred. If BG is negated when BB is
negated (or alternatively BTT asserted), the processor assumes that another master has
taken implicit ownership of the bus. Otherwise, if BG is asserted when BB is negated (or BTT
asserted), the processor assumes implicit ownership of the bus.
If an alternate master loses bus ownership when it is in its implicit ownership state, the pro-
cessor checks TS. If TS is sampled asserted, the processor interprets this as the alternate
master transitioning to its explicit ownership state, and it does not take over bus ownership.
This operation is different from that of the MC68040, in that external arbiters are required to
check for this boundary condition. However, in order for the processor to properly detect this
boundary condition, it is imperative that the TS of all alternate bus masters be tied together
with the processor’s TS signal
7-56
NOTE:
BBO represents the component of BB when driven by the MC68060. BBO is either driven
asserted or three-stated; however, BBO is driven negated for one CLK (as opposed to
BCLK) period before three-stating.
for One CLK, then
Table 7-7. MC68040-Arbitration Protocol State Description
Three-Stated
Not Driven
Not Driven
Not Driven
Not Driven
Not Driven
Asserted
Negated
BBO
Driven at End
Stops Being
Bus Status
Not Driven
Not Driven
Not Driven
Not Driven
Not Driven
of State
Driven
M68060 USER’S MANUAL
Own
Yes
Yes
Yes
No
No
No
No
Alternate Master Implicit Own
Alternate Master Explicit Own
Alternate Master Own
Implicit Ownership
Explicit Ownership
and Snooped
End Tenure
Reset
State
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