MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 229

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Bus Operation
7.14 SPECIAL MODES OF OPERATION
The MC68060 supports the following three operation modes, which are selectively enabled
during processor reset and remain in effect until the next processor reset. Refer to 7.13
Reset Operation for reset timing information. Table 7-10 summarizes the three special
modes and associates them with the appropriate IPLx signal.
7.14.1 Acknowledge Termination Ignore State Capability
The MC68060 provides acknowledge termination ignore state capability to make high-fre-
quency system design easier. This feature defines BCLK edges during which the acknowl-
edge termination signals (TA, TEA, and TRA) are ignored. This feature is enabled if IPL0 is
asserted during reset.
During reset, 16 bits of information (from D15–D0) are registered into the MC68060. These
16 bits define four values of four bits each. Two of the four values are used for read bus
cycles; the other two values are used for write bus cycles. For the read bus cycle, the first
value is the primary ignore state count value. The primary ignore state count value is used
during the first long-word transfer of a line transfer cycle, or the only data transfer for byte,
word, or long-word bus cycles. The second value is the secondary ignore state count value.
The secondary ignore state count value is used during the next three long words for line
transfer cycles, after the first long word has been transferred. Similarly, the two values of the
write bus cycle are defined as a primary ignore state count value and a secondary ignore
state count value, respectively. Figure 7-50 shows the assignment of the four data nibbles
at reset.
At the beginning of a bus cycle, the appropriate primary ignore state count value is loaded
into an internal counter. The counter decrements every BCLK rising edge. As long as the
counter has a non-zero count value, the MC68060 ignores the acknowledge termination sig-
nals. Once the counter reaches zero, the MC68060 asserts SAS for one BCLK period and
begins to sample the acknowledge termination signals and acts accordingly. For byte, word,
or long-word transfers, the bus cycle ends when a valid termination is detected. For line
transfer cycles after the first long-word transfer, the secondary ignore state count value is
7-74
15
Signal
IPL2
IPL1
IPL0
IGNORE STATE COUNT
READ PRIMARY
Value During
Reset Time
Asserted
Asserted
Asserted
Negated
Negated
Negated
12 11
Figure 7-50. Data Bus Usage During Reset
Table 7-10. Special Mode vs. IPLx Signals
Extra Data Write Hold Mode Enabled
Extra Data Write Hold Mode Disabled
Native-MC68060 Acknowledge Termination Protocol
MC68040 Acknowledge Termination Protocol
Acknowledge Termination Ignore State Capability Enabled
Acknowledge Termination Ignore State Capability Disabled
IGNORE STATE COUNT
READ SECONDARY
M68060 USER’S MANUAL
8 7
IGNORE STATE COUNT
WRITE PRIMARY
Action
4
3
IGNORE STATE COUNT
WRITE SECONDARY
MOTOROLA
0