MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 69

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

3.2.2.4 ALTERNATE FUNCTION CODE REGISTERS. The alternate function code regis-
ters contain 3-bit function codes. Function codes can be considered extensions of the 32-bit
logical address that optionally provides as many as eight 4-Gbyte address spaces. The pro-
cessor automatically generates function codes to select address spaces for data and pro-
grams at the user and supervisor modes. Certain instructions use the SFC and DFC
registers to specify the function codes for operations.
3.2.2.5 PROCESSOR CONFIGURATION REGISTER. The PCR is an 32-bit register which
controls the operations of the MC68060 internal pipelines and contains a software readable
revision number. The PCR is shown in Figure 3-5.
Bits 31–16—Identification
Bits 15–8—Revision Number
EDEBUG—Enable Debug Features
Bits 6–2—Reserved by Motorola for future use and must always be zero.
DFP—Disable Floating-Point Unit
ESS—Enable Superscalar Dispatch
MOTOROLA
31
0
These bits are configured with the value which identifies this device as an MC68060.
These bits are ignored when writing to the PCR.
See Appendix A MC68LC060 and Appendix B MC68EC060 for MC68LC060 and
MC68EC060, respectively, identification field values.
Bits 15–8 contain the 8-bit device revision number. The first revision is 00000000. These
bits are ignored when writing to the PCR.
When this bit is set, the MC68060 outputs internal control information on the address bus
(A31–A0) and data bus (D31–D0) during idle bus cycles. This capability is implemented
to support debug of designs that include the MC68060. When this bit is cleared, operation
proceeds in a normal manner and no internal information is output on idle bus cycles. This
bit is cleared at reset.
When this bit is set, the on-chip FPU is disabled and any attempt to execute a floating-
point instruction generates a line F emulator exception. When this bit is cleared, the FPU
executes all floating-point instructions. This bit is cleared at reset. Note that before this bit
is set via the MOVEC instruction, an FNOP must be executed to ensure that all floating-
point exceptions are caught and handled. This would prevent unexpected floating-point
related exceptions to be reported when the FPU is re-enabled at a later time.
When this bit is set, the ability of the MC68060 to execute multiple instructions per
machine cycle is enabled. When this bit is cleared, the ability to execute multiple instruc-
tions per cycle is disabled and the MC68060 operates at a slower rate with lower perfor-
mance. This bit is cleared at reset.
30
0
29
0
28
0
27
0
26
1
25
0
Figure 3-5. Processor Configuration Register
24
0
23
0
22
0
21
1
20
M68060 USER’S MANUAL
1
19
0
18
0
17
0
16
0
15
Revision Number
8
EDEBUG
7
6
Reserved
Integer Unit
2
DFP ESS
1
3-5
0