FWIXP425BD Intel, FWIXP425BD Datasheet - Page 96

• Manufacturer Part Number: FWIXP425BD
• Description: IC NETWRK PROCESSR 533MHZ 492BGA
• Manufacturer: Intel

Specifications of FWIXP425BD

• Processor Type: Network
• Features: XScale Core
• Speed: 533MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 852279

Intel
Electrical Specifications
Table 54.
96
®
IXP42X Product Line and IXC1100 Control Plane Processor
Motorola* Multiplexed Mode Values
NOTES:
1. The EX_ALE signal is extended form 1 to 4 cycles based on the programming of the T1 timing parameter.
2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device.
3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data
4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or
5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and
6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
7. One cycle is the period of the Expansion Bus clock.
8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
9. Timing tests were performed with a 70-pF capacitor to ground.
Symbol
T
T
T
ale2addrhold
T
dholdafterds
The parameter Tale2addrhold is fixed at 1 cycle
strobe (read or write) to an external device.
write) to an external device. Data will be available during this time as well.
data (during a write) will be held.
expansion interface.
synchronous mode.
T
T
T
dval2valds
ale2valcs
T
T
alepulse
dspulse
rdsetup
rdhold
recov
Parameter
Pulse width of ALE (ADDR is valid at the rising edge of ALE)
Valid address hold time after from falling edge of ALE
Write data valid prior to EXP_MOT_DS_N falling edge
Pulse width of the EXP_MOT_DS_N
Valid data after the rising edge of EXP_MOT_DS_N
Valid chip select after the falling edge of ALE
Data valid required before the rising edge of EXP_MOT_DS_N
Data hold required after the rising edge of EXP_MOT_DS_N
Time needed between successive accesses on expansion
interface.
Min.
5.3
1
1
1
1
1
1
2
1
Max.
14.7
16
16
4
1
4
4
4
Units
Cycles 1, 2,
Cycles
Cycles 1,
Cycles 3,
Cycles 4,
Cycles 5,
Cycles
ns
ns
Datasheet
Notes
7
6
7
7
7
7
7