CS4202-JQZ Cirrus Logic Inc, CS4202-JQZ Datasheet - Page 13

• Manufacturer Part Number: CS4202-JQZ
• Description: IC AC 97 W/HEADPHONE AMP 48TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 18, 20 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPS
• Interface Type: Serial (5-Wire, I2S)
• Resolution: 18 bit, 20 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC/1 DAC
• Supply Current: 10 mA
• Thd Plus Noise: - 84 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1181

2.2
The CS4202 contains a set of AC ’97 compliant
control registers, and a set of Cirrus Logic defined
control registers. These registers control the basic
functions and features of the CS4202. Read access-
es of the control registers by the AC ’97 controller
are accomplished with the requested register index
in Slot 1 of a SDATA_OUT frame. The following
SDATA_IN frame will contain the read data in Slot
2. Write operations are similar, with the register in-
dex in Slot 1 and the write data in Slot 2 of a
SDATA_OUT frame. The function of each input
and output frame is detailed in Section 3, AC-Link
Frame Definition. Individual register descriptions
are found in Section 4, Register Interface.
2.3
The sample rate converters (SRC) provide high ac-
curacy digital filters supporting sample frequencies
other than 48 kHz to be captured from the CS4202
or played from the controller. AC ’97 requires sup-
port for two audio rates (44.1 and 48 kHz). In addi-
tion, the Intel
specification [9] requires support for five more au-
dio rates (8, 11.025, 16, 22.05, and 32 kHz). The
CS4202 supports all these rates, as shown in
Table 10 on page 32.
2.4
The CS4202 input and output mixers are illustrated
in Figure 8. The stereo input mixer sums together
DS549PP2
Control Registers
Sample Rate Converters
Mixers
®
I/O Controller Hub (ICHx)
the analog inputs to the CS4202 according to the
settings in the volume control registers. The stereo
output mixer sums the output of the stereo input
mixer with the PC_BEEP and PHONE signals. The
stereo output mix is then sent to the LINE_OUT
and HP_OUT pins of the CS4202. The mono out-
put mixer generates a monophonic sum of the left
and right audio channels from the stereo input mix-
er. The mono output mix is then sent to the
MONO_OUT pin on the CS4202.
2.5
The input multiplexer controls which analog input
is sent to the ADCs. The output of the input mux is
converted to stereo 18-bit digital PCM data and
transmitted to the controller by means of the
AC-link SDATA_IN signal.
2.6
The CS4202 volume registers control analog input
levels to the input mixer and analog output levels,
including the master volume level. The PC_BEEP
volume control uses 3 dB steps with a range of 0 dB
to -45 dB attenuation. All other analog volume con-
trols use 1.5 dB steps. The analog inputs have a
mixing range of +12 dB signal gain to -34.5 dB sig-
nal attenuation. The analog output volume controls
have a range of 0 dB to -46.5 dB attenuation for
LINE_OUT, HP_OUT and MONO_OUT.
Input Mux
Volume Control
CS4202
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