CS4202-JQZ Cirrus Logic Inc, CS4202-JQZ Datasheet - Page 38

• Manufacturer Part Number: CS4202-JQZ
• Description: IC AC 97 W/HEADPHONE AMP 48TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 18, 20 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPS
• Interface Type: Serial (5-Wire, I2S)
• Resolution: 18 bit, 20 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC/1 DAC
• Supply Current: 10 mA
• Thd Plus Noise: - 84 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1181

4.24
DPC
10dB
CRST
GPOC
LOSM
Default
38
D15
0
Misc. Crystal Control Register (Index 60h)
D14
0
D13
0
is ‘set’, the CS4202 will mute all analog outputs for the duration of loss of SYNC. If this bit is
‘cleared’, the mixer will continue to function normally during loss of SYNC. The CS4202 ex-
pects to sample SYNC ‘high’ for 16 consecutive BIT_CLK periods and then ‘low’ for 240 con-
secutive BIT_CLK periods, otherwise loss of SYNC becomes true.
DAC Phase Control. This bit controls the phase of the PCM stream sent to the DACs (after
SRC). When ‘cleared’ the phase of the signal will remain unchanged. When this bit is ‘set’,
each PCM sample will be inverted before being sent to the DACs.
Microphone 10 dB Boost. When ‘set’, the 10dB bit enables an additional boost of 10 dB on
the selected microphone input. In combination with the 20dB boost bit in the Microphone Vol-
ume Register (Index 0Eh) this bit allows for variable boost from 0 dB to +30 dB in steps of
10 dB.
Force Cold Reset. The CRST bit is used as an override to the New Warm Reset behavior
defined during PR4 powerdown. If this bit is ‘set’, an active RESET# signal will force a Cold
Reset to the CS4202 during a PR4 powerdown.
General Purpose Output Control. The GPOC bit specifies the mechanism by which the status
of a General Purpose Output pin can be controlled. If this bit is ‘cleared’, the GPO status is
controlled through the standard AC ’97 method of setting the appropriate bits in output
Slot 12. If this bit is ‘set’, the GPO status is controlled through the GPIO Pin Status Register
(Index 54h).
Loss of SYNC Mute Enable. The LOSM bit controls the loss of SYNC mute function. If this bit
0003h
DPC
D12
D11
0
D10
0
D9
Reserved
D8
10dB CRST
D7
D6
D5
0
D4
0
GPOC
D3
D2
Reserved
CS4202
D1
DS549PP2
LOSM
D0