CS4202-JQZ Cirrus Logic Inc, CS4202-JQZ Datasheet - Page 59

• Manufacturer Part Number: CS4202-JQZ
• Description: IC AC 97 W/HEADPHONE AMP 48TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 18, 20 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPS
• Interface Type: Serial (5-Wire, I2S)
• Resolution: 18 bit, 20 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC/1 DAC
• Supply Current: 10 mA
• Thd Plus Noise: - 84 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1181

AFLT1 - Left ADC Channel Antialiasing Filter, Input, Pin 29
AFLT2 - Right ADC Channel Antialiasing Filter, Input, Pin 30
HPCFG - Headphone Configuration, Input, Pin 31
AC-Link Pins
RESET# - AC ’97 Chip Reset, Input, Pin 11
SYNC - AC-Link Serial Port Sync Pulse, Input, Pin 10
BIT_CLK - AC-Link Serial Port Master Clock, Input/Output, Pin 6
SDATA_OUT - AC-Link Serial Data Input Stream to AC ’97, Input, Pin 5
SDATA_IN - AC-Link Serial Data Output Stream from AC ’97, Output, Pin 8
DS549PP2
This pin needs a 1000 pF NPO capacitor connected to analog ground.
This pin needs a 1000 pF NPO capacitor connected to analog ground.
This pin is the configuration control for the signal routing to the headphone amplifier. If this pin is left
floating, the LINE_OUT and HP_OUT pins function as defined in the AC ’97 specification. If the HPCFG
pin is grounded, the HP_OUT pins behave as a buffered line output. In addition, the LINE_OUT pins are
muted, the control register for the headphone output will be the Master Output Volume Register (Index
02h), and PC_BEEP is routed to the HP_OUT pins during RESET. The HPCFG pin is internally pulled
up to the analog supply voltage.
This active low signal is the asynchronous Cold Reset input to the CS4202. The CS4202 must be reset
before it can enter normal operating mode.
SYNC is the serial port timing signal for the AC-link. Its period is the reciprocal of the maximum sample
rate, 48 kHz. The signal is generated by the controller and is synchronous to BIT_CLK. SYNC is an
asynchronous input when the CS4202 is configured as a primary codec and is in a PR4 powerdown
state. A series terminating resistor of 47 Ω should be connected on this signal close to the controller.
This input/output signal controls the master clock timing for the AC-link. In primary mode, this signal is a
12.288 MHz output clock derived from either a 24.576 MHz crystal or from the internal PLL based on
the XTL_IN input clock. When the CS4202 is in secondary mode, this signal is an input which controls
the AC-link serial interface and generates all internal clocking including the AC-link serial interface
timing and the analog sampling clocks. A series terminating resistor of 47 Ω should be connected on
this signal close to the CS4202 in primary mode or close to the BIT_CLK source in secondary mode.
This input signal receives the control information and digital audio output streams. The data is clocked
into the CS4202 on the falling edge of BIT_CLK. A series terminating resistor of 47 Ω should be
connected on this signal close to the controller.
This output signal transmits the status information and digital audio input streams from the ADCs. The
data is clocked out of the CS4202 on the rising edge of BIT_CLK. A series terminating resistor of 47 Ω
should be connected on this signal close to the CS4202.
CS4202
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