CS4202-JQZ Cirrus Logic Inc, CS4202-JQZ Datasheet - Page 42

• Manufacturer Part Number: CS4202-JQZ
• Description: IC AC 97 W/HEADPHONE AMP 48TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 18, 20 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPS
• Interface Type: Serial (5-Wire, I2S)
• Resolution: 18 bit, 20 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC/1 DAC
• Supply Current: 10 mA
• Thd Plus Noise: - 84 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1181

5. SERIAL DATA PORTS
5.1
The CS4202 implements two serial data output
ports that can be used for multi-channel expansion.
Each serial port consists of 4 signals: MCLK,
SCLK, LRCLK, and SDATA. The existing 256 Fs
BIT_CLK will be used as MCLK. The clock pins
are shared between all the serial ports with only the
SDATA pins being separate; SDOUT for the first
output port, and SDO2 for the second output port.
Serial data is transmitted on these ports every
AC-link frame.
The serial data port is controlled by the SDEN,
SDSC, and SDO2 bits in the Serial Port Control
Register (Index 6Ah). All the serial data port pins
are multiplexed with other functions and cannot be
used unless the other function is disabled or pow-
ered down; see Section 7, Exclusive Functions.
Some audio DACs can run in an internal SCLK
mode where SCLK is internally derived from
MCLK and LRCLK. In this case, SCLK generation
in the CS4202 is optional.
A feature has been designed into the CS4202 that
allows the phase of the internal DACs to be re-
versed. This DAC phase reversal is controlled by
42
Overview
GPIO1/SDOUT
GPIO0/LRCLK
LINE_OUT_R
GPIO4/SDO2
LINE_OUT_L
EAPD/SCLK
BIT_CLK
35
36
44
47
43
6
34
Figure 10. Serial Data Port: Six Channel Circuit
1
2
3
4
1
2
3
4
SDATA
DEM#/SCLK
LRCK
MCLK
SDATA
LRCK
MCLK
DEM#/SCLK
CS4334
CS4334
AOUTR
AOUTR
AOUTL
AOUTL
8
5
8
5
1000pF
270K
270K
AGND
AGND
AGND
1000pF
270K
270K
the DPC bit in the Misc. Crystal Control Register
(Index 60h). This feature is necessary since the
phase response for external DACs is unknown and
the phase response of the internal DACs can vary
depending on the path determined by the DDM bit
in the AC Mode Control Register (Index 5Eh) and
the output (LINE_OUT or HP_OUT) being used.
This feature guarantees that all DACs in a system
have the same phase response, maintaining the ac-
curacy of spatial cues.
Please note the data sent to the serial ports is
straight from the AC-link. There is no SRC and no
volume control available on this data, so it is the re-
sponsibility of the controller or host software to
provide this functionality if desired.
5.2
For multi-channel expansion, the two serial data
output ports are used to send AC-link data to one or
two external stereo DACs to support up to a total of
six channels. The first serial port takes the digital
audio data from the SDOUT slots. The second seri-
al port takes the digital audio data from the SDO2
slots. See Table 8 on page 30 for the actual slots
used depending on configuration. Figure 10 shows
a six channel application using the CS4202.
+
+
+
+
ELEC
ELEC
ELEC
ELEC
10uF
10uF
10uF
10uF
+
+
ELEC
ELEC
10uF
10uF
Multi-Channel Expansion
47K
47K
AGND
AGND
47K
47K
560
560
560
560
220K
AGND
2700pF 2700pF
2700pF 2700pF
220K
AGND
AGND
Left Front
Right Front
Left Surround
Right Surround
Center
LFE
CS4202
DS549PP2