CS4202-JQZ Cirrus Logic Inc, CS4202-JQZ Datasheet - Page 44

• Manufacturer Part Number: CS4202-JQZ
• Description: IC AC 97 W/HEADPHONE AMP 48TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 18, 20 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPS
• Interface Type: Serial (5-Wire, I2S)
• Resolution: 18 bit, 20 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC/1 DAC
• Supply Current: 10 mA
• Thd Plus Noise: - 84 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1181

6. SONY/PHILIPS DIGITAL
The S/PDIF digital output is used to interface the
CS4202 to consumer audio equipment external to
the PC. This output provides an interface for stor-
ing digital audio data or playing digital audio data
to digital speakers. Figure 15 illustrates the circuits
necessary for implementing the IEC-958 optical or
consumer interface. For further information on
S/PDIF operation see application note AN22: Over-
view of Digital Audio Interface Data Structures [3].
For further information on S/PDIF recommended
transformers see application note AN134: AES and
S/PDIF Recommended Transformers [4].
7. EXCLUSIVE FUNCTIONS
Some of the digital pins on the CS4202 have mul-
tiplexed functionality. These functions are mutual-
ly exclusive and cannot be requested at the same
time. The following pairs of functions are mutually
exclusive:
•
44
SPDIF_OUT
INTERFACE (S/PDIF)
GPIO and Serial Data Port (GPIO0 pin is
shared with LRCLK pin, GPIO1 pin is shared
DVdd
R
R
1
2
247.5 Ω
107.6 Ω
3.3V
93.75 Ω
375 Ω
5V
R
1
DGND
R
2
Figure 15. S/PDIF Output
T
1
J1
•
Use of the GPIO0/LRCLK, GPIO1/SDOUT, and
GPIO4/SDO2 pins for serial data port has priority
over their GPIO functionality. There is no priority
assigned to the other exclusive function. A function
currently in use must be disabled or powered down
before the corresponding exclusive function can be
enabled. The following control bits for these func-
tions will behave differently than normal bits: the
EAPD bit in the Powerdown Control/Status Regis-
ter (Index 26h), the GC[4,1:0] bits in the GPIO Pin
Configuration Register (Index 4Ch), and the
SDO2, and SDSC bits in the Serial Port Control
Register (Index 6Ah). These bits can become
read-only bits if they control a feature that is cur-
rently unavailable because the corresponding ex-
clusive feature is already in use, or the
corresponding master control for this feature is not
set.
with SDOUT pin, and GPIO4 pin is shared with
SDO2 pin)
EAPD and Serial Data Port Serial Clock
(EAPD pin is shared with SCLK pin)
0.1 µ F
+5V_PCI
DGND
SPDIF_OUT
8.2 kΩ
4
3
2
1
TOTX-173
CS4202
DS549PP2
5
6
DGND
DGND