CS4202-JQZ Cirrus Logic Inc, CS4202-JQZ Datasheet - Page 22

• Manufacturer Part Number: CS4202-JQZ
• Description: IC AC 97 W/HEADPHONE AMP 48TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4202-JQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 18, 20 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPS
• Interface Type: Serial (5-Wire, I2S)
• Resolution: 18 bit, 20 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC/1 DAC
• Supply Current: 10 mA
• Thd Plus Noise: - 84 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1181

4.1
ID8
ID7
ID4
Default
4.2
Mute
ML[5:0]
MR[5:0]
Default
If the HPCFG pin is left floating, register 02h controls the Master Output Volume and register 04h controls the Head-
phone Output Volume. If the HPCFG pin is tied ‘low’, register 02h controls the Headphone Volume and register 04h
is a read-only register and always returns 0000h when ‘read’.
22
Any write to this register causes a Register Reset of the audio control (Index 00h - 3Ah) and Cirrus Logic defined
(Index 5Ah - 7Ah) registers. A read from this register returns configuration information about the CS4202.
Mute
D15
D15
0
Reset Register (Index 00h)
Analog Mixer Output Volume Registers (Index 02h - 04h)
D14
D14
0
0
ML5
D13
D13
0
18-bit ADC Resolution. The ID8 bit is ‘set’, indicating this feature is present.
20-bit DAC resolution. The ID7 bit is ‘set’, indicating this feature is present.
Headphone Out. The ID4 bit is ‘set’, indicating this feature is present. The state of this bit de-
pends on the state of the HPCFG pin.
0190h. The data in this register is read-only data.
Output Mute. Setting this bit mutes the LINE_OUT_L/R or HP_OUT_L/R output signals.
Output Volume Left. These bits control the left output volume. Each step corresponds to 1.5
dB gain adjustment, with a total available range from 0 dB to -46.5 dB attenuation. Setting the
ML5 bit sets the left channel attenuation to -46.5 dB by forcing ML[4:0] to a ‘1’ state. ML[5:0]
will read back 011111 when ML5 has been ‘set’. See Table 2 for further details.
Output Volume Right. These bits control the right output volume. Each step corresponds to
1.5 dB gain adjustment, with a total available range from 0 dB to -46.5 dB attenuation. Setting
the MR5 bit sets the right channel attenuation to -46.5 dB by forcing MR[4:0] to a ‘1’ state.
MR[5:0] will read back 011111 when MR5 has been ‘set’. See Table 2 for further details.
8000h. This value corresponds to 0 dB attenuation and Mute ‘set’.
ML4
D12
D12
0
ML3
D11
D11
0
Table 2. Analog Mixer Output Attenuation
ML2
D10
D10
Mx5 - Mx0
0
000000
000001
100000
011111
111111
Write
…
...
ML1
D9
D9
0
ML0
Mx5 - Mx0
ID8
D8
D8
000000
000001
011111
011111
011111
Read
…
...
ID7
D7
D7
0
-46.5 dB
-46.5 dB
-46.5 dB
-1.5 dB
D6
D6
Level
0
0
Gain
0 dB
...
...
MR5
D5
D5
0
MR4
ID4
D4
D4
MR3
D3
D3
0
MR2
D2
D2
0
CS4202
MR1
D1
D1
0
DS549PP2
MR0
D0
D0
0