DP83955AV National Semiconductor, DP83955AV Datasheet - Page 13

• Manufacturer Part Number: DP83955AV
• Description: IC CTRLR RIC REPEATER 100-PQFP
• Manufacturer: National Semiconductor
• Series: LERIC™r

Specifications of DP83955AV

• Controller Type: LitE Repeater Interface Controller
• Voltage - Supply: 5V
• Current - Supply: 250mA
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Interface: -
• Other names: *DP83955AV

INTER-LERIC BUS PINS (Continued)
POWER AND GROUND PINS
EXTERNAL DECODER PINS
Name
IRE
IRC
COLN
CLK
V
GND
RXM
Pin
CC
3 0 Pin Description
Note TT
OD
C
O
B
Z
Driver
I
Type
e
e
e
e
e
e
e
TT
TT
TT
TT
TT
TTL compatible
Bi-directional
CMOS compatible
Open Drain
Input
Output
TRI-STATE
B Z
B Z
B Z
I O
O
I
Inter-LERIC Enable When asserted as an output this signal provides an activity framing enable for the
serial data stream The signal is asserted by a LERIC when it is receiving data from one of its network
segments The default condition of this signal is to be an input In this state it may be driven by other
devices on the Inter-LERIC bus
Inter-LERIC Clock When asserted as an output this signal provides a clock signal for the serial data
stream Data (IRD) is changed on the falling edge of the clock The signal is asserted by a LERIC when it
is receiving data from one of its network segments The default condition of this signal is to be an input
When an input IRD is sampled on the rising edge of the clock In this state it may be driven by other
devices on the Inter-LERIC bus
COLlision on Port N This denotes that a collision is occurring on the port receiving the data packet (Port
N) The default condition of this signal is to be an input In this state it may be driven by other devices on
the Inter-LERIC bus
20 MHz Clock Input This input is used to generate the LERIC’s timing reference for the state machines
and phase lock loop decoder The 20 MHz clock should have a 0 01% frequency tolerance and 40%–
60% duty cycle or better (i e 50 50 duty cycle)
Positive Supply
Negative Supply
Receive Data Manchester Format This output makes the data in Manchester format received by port
N available for test purposes If not used for testing this pin should be left open
(Continued)
13
Description