DP83955AV National Semiconductor, DP83955AV Datasheet - Page 34

• Manufacturer Part Number: DP83955AV
• Description: IC CTRLR RIC REPEATER 100-PQFP
• Manufacturer: National Semiconductor
• Series: LERIC™r

Specifications of DP83955AV

• Controller Type: LitE Repeater Interface Controller
• Voltage - Supply: 5V
• Current - Supply: 250mA
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Interface: -
• Other names: *DP83955AV

Figure 5-11
5 0 Functional Description
259 Output
259 Addr S(2 –0)
LERIC Port Number
LERIC D0
LERIC D1
LERIC D2
LERIC D3
LERIC D4
Note This shows the LED Output Functions for the LED Drivers when 74LS259s are used
Description of Data Freeze Strobe (DFS) Pin Operation
DFS has been implemented to assist the user to provide
partial hub management statistics on a per packet per port
basis The DFS signal is asserted active high at the end of
the transmission of each packet and the status of that
packet is frozen on the LEDs until the beginning of the next
received packet or for a maximum of 30 ms as is shown in
The DFS signal can be used to latch the LED information
into a shared buffer which acts as an external flag register
and can be used as a mechanism to trap events
ACOL
LINK
BDPOL
e
e
e
Port Link COL
Any Port Collision AREC
Bad (inverse) Polarity of received data
FIGURE 5-11 DFS Operation
e
APART
Port Collision REC
ACOL
AREC
JAB
000
Q0
e
Any Port Reception JAB
FIGURE 5-10 Maximum Mode LED Definitions
1 (AUI)
PART
REC
COL
001
Q1
e
(Continued)
Port Reception PART
TL F 11240–41
BDPOL
PART
LINK
REC
COL
010
Q2
2
e
Any Port Jabbering
34
e
74LS259 Latch Inputs
Port Partitioned
BDPOL
PART
LINK
Processor Access Cycles
Access to the LERIC’s on-chip registers is made via its
processor interface This utilizes a conventional non-multi-
plexed address (four bit) and data (four bit) bus This bus is
also used to provide data and address information to off
chip LED display latches during display update cycles While
performing these cycles the LERIC behaves as a master of
its data bus Consequently a TRI-STATE bi-directional bus
transceiver (e g 74LS245) must be placed between the
LERIC and any processor bus Internally each of the
LERIC’s registers is 8 bits however there are four bits of
data pins (D(3 0)) Each register is accessed on a nibble
basis (4 bits at a time) D(7) of the address pins D(7 4) se-
lects the upper and lower nibbles as described in Section 7
To access the LERIC’s registers the processor requests a
register access by asserting the read (RD) or write (WR)
input strobes The LERIC responds by finishing any current
display update cycle and asserts the TRI-STATE buffer en-
able signal (BUFEN) If the processor cycle is a write cycle
then the LERIC’s buffers are disabled to prevent contention
In order to interface to the LERIC a PAL device may be
used to perform the following operations
1 Generate the LERIC’s read and write strobes
2 Control the direction signal for the 74LS245
An example of the processor and display interfaces is
shown in Figure 5-12
COL
REC
011
Q3
3
BDPOL
PART
LINK
COL
REC
100
Q4
4
BDPOL
PART
LINK
COL
REC
101
Q5
5
BDPOL
PART
LINK
REC
COL
110
Q6
6
BDPOL
PART
LINK
COL
REC
111
A7
7