DP83955AV National Semiconductor, DP83955AV Datasheet - Page 18

• Manufacturer Part Number: DP83955AV
• Description: IC CTRLR RIC REPEATER 100-PQFP
• Manufacturer: National Semiconductor
• Series: LERIC™r

Specifications of DP83955AV

• Controller Type: LitE Repeater Interface Controller
• Voltage - Supply: 5V
• Current - Supply: 250mA
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Interface: -
• Other names: *DP83955AV

5 0 Functional Description
updates are completely autonomous and merely require SSI
logic devices to drive the display devices usually made up
of light emitting diodes LEDs The status display is very
flexible allowing the user to choose those indicators appro-
priate for the specification of the equipment The Display
Frozen Strobe (DFS) may be used to latch the various indi-
cators which are frozen at the end of the activity The LED
display will be frozen for 30 ms after the end of the activity
or until a new activity has started whichever is shorter Note
that the complete LED display cycle for all the ports takes
approximately 1 6 s
Processor Interface
The LERIC’s processor interface allows connection to a
system processor (or a simple read write logic interface)
Data transfer occurs via a 4-bit bidirectional data bus and 4-
bit address bus Display update cycles and processor ac-
cesses occur utilizing the same bus An on-chip arbiter in
the processor display block schedules and controls the ac-
cesses and ensures the correct information is written into
the display latches During the display update cycles the
LERIC behaves as a master of its bus This is the default
state of the bus Consequently a TRI-STATE buffer must be
placed between the LERIC and the system processor’s data
bus This ensures bus contention is avoided during simulta-
neous display update cycles and processor accesses of
other devices on the system bus When the processor ac-
cesses a LERIC register the LERIC enables the data buffer
and selects the operation either input to or output from the
data pins
5 2 DESCRIPTION OF REPEATER OPERATIONS
In order to implement a multi-chip repeater system which
behaves as though it were a single logical repeater special
consideration must be paid to the data path used in packet
repetition For example where in the path are specific oper-
ations such as Manchester decoding and elasticity buffering
performed Also the system’s state machines which utilize
available network activity signals must be able to accom-
modate the various packet repetition and collision scenarios
detailed in the IEEE 802 3 repeater specification
(Continued)
18
italics The IEEE state diagram is shown in Figure 5-2 the
5-1
The LERIC contains two types of interacting state ma-
chines These are
1 Port State Machines (PSMs) Every network attachment
2 Main State Machine (MSM) This state machine controls
Repeater Port and Main State Machines
These two state machines are described in the following
sections Reference is made to expressions used in the
IEEE 802 3 Repeater specification For the precise defini-
tion of these terms please refer to the IEEE specifications
To avoid confusion with the LERIC’s implementation where
references are made to repeater states or terms as de-
scribed in the IEEE specification these items are written in
Inter-LERIC Inter-RIC bus state diagram is shown in Figure
FIGURE 5-1 Inter-LERIC Inter-RIC Bus State Diagram
has its own PSM
the shared functional blocks as shown in the block dia-
gram Figure 4-1
TL F 11240 – 7