DP83955AV National Semiconductor, DP83955AV Datasheet
DP83955AV
Specifications of DP83955AV
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DP83955AV Summary of contents
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... DP83955 are changed to unidirectional signals on DP83956 and one more signal is added to DP83956 to accommodate the addi- tion of bus transceivers for cascading a greater number of LERICs in large repeater applications 1 0 System Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation Inter-LERIC TM Inter-RIC TM LERIC ...
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SYSTEM DIAGRAM 2 0 CONNECTION DIAGRAMS 3 0 PIN DESCRIPTION 4 0 BLOCK DIAGRAM 5 0 FUNCTIONAL DESCRIPTION 5 1 Overview of LERIC Functions 5 2 Description of Repeater Operations 5 3 Examples of Packet Repetition Scenarios 5 ...
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Connection Diagrams (Configured as Port 1 Full AUI and Ports 2– 7 Twisted-Pair) Pin Name Pin No Pin Name TXO4 1 TXO7 a a TXO4P 2 TXO7 b b GND 3 TXO7P RXI7 a CC ...
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Connection Diagrams (Continued) (Configured as Port 1 Full AUI Ports 2– 3 AUI and Ports 4– 7 Twisted-Pair) Pin Name Pin No Pin Name TXO4 1 TXO7 a a TXO4P 2 TXO7 b b GND 3 TXO7P a ...
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Connection Diagrams (Continued) (Configured as Port 1 Full AUI Ports 2– 5 AUI and Ports 6– 7 Twisted-Pair) Pin Name Pin No Pin Name TX4 1 TXO7 a a TX4 2 TXO7 b b GND 3 TXO7P a ...
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Connection Diagrams (Continued) (Configured as Port 1 Full AUI Ports 2– 7 AUI) Pin Name Pin No Pin Name TX4 1 TX7 a a TX4 2 CD7 b b GND 3 CD7 RX7 b CC ...
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Connection Diagrams (Configured as Port 1 Full AUI Ports 2 – 7 Twisted-Pair) Pin Name Pin No Pin Name Pin No GND PKEN V 3 IRE CC RXI6 4 ACTNS a RXI6 5 ...
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Connection Diagrams (Configured as Port 1 Full AUI Ports 2– 3 AUI and Ports 4– 7 Twisted-Pair) Pin Name Pin No Pin Name Pin No GND PKEN V 3 IRE CC RXI6 4 ...
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Connection Diagrams (Configured as Port 1 Full AUI Ports 2– 5 AUI and Ports 6– 7 Twisted-Pair) Pin Name Pin No Pin Name Pin No GND PKEN V 3 IRE CC RXI6 4 ...
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Connection Diagrams (Configured as Port 1 Full AUI Ports 2– 7 AUI) Pin Name Pin No Pin Name Pin No GND PKEN V 3 IRE CC RX6 4 ACTNS b RX6 5 ACTND ...
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Pin Description Driver Pin Name Type NETWORK INTERFACE PINS (On-Chip Transceiver Mode) RXI2 to RXI7 RXI2 to RXI7 TXOP2 to TXOP7 TXO2 to TXO7 TXO2 to ...
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Pin Description (Continued) Pin Driver I O Name Type PROCESSOR BUS PINS STR C O Display Update STRobe This signal controls the latching of display data for network ports into the off chip display latches During processor access ...
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Pin Description (Continued) Pin Driver I O Name Type INTER-LERIC BUS PINS (Continued) IRE Inter-LERIC Enable When asserted as an output this signal provides an activity framing enable for the serial data stream The signal ...
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Pin Description (Continued) Pin Pin Driver Name Type 30 ACTN OD B ACTivity on Port N This is a bidirectional signal The LERIC asserts this signal when data or collision information is received from one ...
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Block Diagram DP83955 BLOCK DIAGRAM 15 ...
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Block Diagram (Continued DP83956 BLOCK DIAGRAM 16 ...
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Functional Description The IEEE 802 3 repeater specification details a number of functions a repeater system must perform These require- ments allied with a need for the implementation to be multi- port strongly favors the choice of a ...
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Functional Description updates are completely autonomous and merely require SSI logic devices to drive the display devices usually made up of light emitting diodes LEDs The status display is very flexible allowing the user to choose those indicators ...
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Functional Description FIGURE 5-2 IEEE Repeater Main State Diagram (Continued 11240– 8 ...
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Functional Description Port State Machine (PSM) There are two primary functions for the PSM as follows 1 Control the transmission of repeated data and jam sig- nals over the attached segment 2 Decide whether a port will be ...
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Functional Description ACKI Function Input signal to the PSM arbitration chain This chain is employed to identify PORT N and PORT M Note A LERIC which contains PORT N or PORT M may be identified by its ACKO ...
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Functional Description Methods of LERIC Cascading In order to build multi-LERIC repeaters PORT N and PORT M identification must be performed across all the LERICs in the system Inside each LERIC the PSMs are arranged in a logical ...
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Functional Description Note 1 The activity shown on RX represents the transmitted signal (Continued) after being looped back by the attached transceiver A1 FIGURE 5-4 Data Repetition 11240 – 10 ...
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Functional Description The repeater is stimulated into activity by the data signal received by port B1 The LERICs in the system are alerted to forthcoming repeater operation by the falling edges on the ACKI –ACKO daisy chain and ...
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Functional Description Note 1 SEND PREAMBLE SEND SFD SEND DATA (Continued) FIGURE 5-5 Receive Collision 11240 – 11 ...
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Functional Description Transmit Collisions A transmit collision is a collision that is detected upon a segment to which the repeater system is transmitting The port state machine monitoring the colliding segment asserts the ANYXN bus signal The assertion ...
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Functional Description (Continued) FIGURE 5-6 Transmit Collision 11240 – 12 ...
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Functional Description Jabber Protection A repeater is required to disable transmit activity if the length of its current transmission reaches the jabber protect limit This is defined by the IEEE specification’s Tw3 time The repeater disables output for ...
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Functional Description 5 4 DESCRIPTION OF HARDWARE CONNECTION FOR CASCADING DP89355 on the Inter-LERIC Bus When considering the hardware interface the Inter-LERIC bus may be viewed as consisting of three groups of signals 1 Port ...
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Functional Description TABLE 5-2 Pin Definitions for Options in the MLOAD Operation Pin Programming Effect When Effect When Name Function Bit BYPAS1 D1 BYPAS2 D2 Resv Not Permitted D3 EPOLSW Not Selected D4 Resv Not ...
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Functional Description 5 6 PROCESSOR AND DISPLAY INTERFACE HARDWARE CONNECTION Display Update Cycles The LERIC possesses control logic and interface pins which may be used to provide status information concerning activi the attached network segments and ...
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Functional Description TABLE 5-4 Status Display Pin Functions in Maximum Mode Signal Pin Name D0 Provides status information concerning the Link Integrity status of 10BASE-T segments This signal should be connected to the data inputs of the chosen ...
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Functional Description (Continued) 33 ...
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Functional Description 259 Output Q0 Q1 000 001 259 Addr S(2 –0) 1 (AUI) LERIC Port Number LERIC D0 ACOL LERIC D1 AREC COL LERIC D2 JAB REC LERIC D3 APART PART LERIC D4 Note This shows the ...
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Functional Description FIGURE 5-12 Processor Connection Diagram 6 0 Port Block Functions The LERIC has 7 port logic blocks (one for each network connection) In addition to the packet repetition operations already described the port block performs two ...
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Port Block Functions (Continued) For typical Filter-Transformer-Choke Modules refer to ETHERNET MAGNETIC VENDORS In addition to these the Valor FL1085 is recommended for HCT Drivers FIGURE 6-1 Port Connection to a 10BASE-T Segment The above diagrams show a ...
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Port Block Functions (Continued SEGMENT PARTITION Each of the LERIC ports has a dedicated state machine to perform the functions defined by the IEEE partition algo- rithm as shown in Figure 6-3 To allow users to ...
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Port Block Functions (Continued) FIGURE 6-3 IEEE Segment Partition Algorithm 11240– 19 ...
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LERIC Registers 7 1 LERIC REGISTER ADDRESS MAP The LERIC’s registers may be accessed by applying the required address to the four register address (D(7 4)) input pins Pin D(7) makes the selection between the upper and Address ...
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LERIC Registers (Continued LERIC STATUS REGISTER This register contains real time information concerning the operation of the LERIC D(3) D(2) D(1) D(0) Resv Resv Resv Resv Symbol Bit R W ACOL D(0) R Any Collisions 0 ...
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LERIC Registers (Continued PORT STATUS AND CONFIGURATION REGISTERS D(3) D(2) D(1) D(0) DISPT Resv POL SQL Symbol Bit R W GDLNK D( Good Link 0 Link pulses are being received by the port 1 ...
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... Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Input Voltage ( Output Voltage ( OUT Specifications Symbol Description PROCESSOR LED TWISTED-PAIR PORTS AND INTER-LERIC INTERFACES V Minimum High Level ...
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DC Specifications Symbol Description PSEUDO AUI (PORTS 2–7) V Differential Output POD Voltage ( Differential Output Voltage POB Imbalance ( Undershoot Voltage ( Differential Squelch PDS Threshold ...
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Switching Characteristics RECEIVE TIMING-10BASE-T PORTS Receive activity propagation start up and end delays for ports in 10BASE-T mode Symbol Number rxaackol T3t RX Active to ACKO Low rxiackoh T4t RX Inactive to ACKO High (Note 1) rxaactnl T5t ...
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Switching Characteristics TRANSMIT TIMING 10BASE-T PORTS Receive activity propagation start up and end delays for ports in 10BASE-T mode Symbol Number actnltxa T15t ACTN Low to TX Active clkitxa T16t CLOCK Active (Note 1) Note ...
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Switching Characteristics RECEIVE COLLISION TIMING Symbol Number cdacolna T32a CD Active to COLN Low cdicolni T33a CD Inactive to COLN High colnljs T39 COLN Low to Start of JAM colnhje T40 COLN High to End of JAM(Note 1) ...
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Switching Characteristics COLLISION TIMING ALL PORTS Symbol Number anylmin T34 ANYXN Low Time anyhtxai T35 ANYXN High All Inactive anylsj T38 ANYXN Low to Start of JAM COLLISION TIMING ALL PORTS Symbol Number actnhtxi T36 ...
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Switching Characteristics RESET TIMING Symbol Number resdats T61 resdath T62 reslbufl T63 reshbufh T64 resw T65 LED STROBE TIMING Symbol Number stradrs T66 strdats T67 strdath T68 strw T69 (Continued) Parameter Min Data Setup 20 Data Hold 20 ...
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Switching Characteristics REGISTER READ TIMING Symbol Number rdadrs T80 Address Setup from BUFEN Low rdadrh T81 Address Hold after RD High rdlbufl T82 RD Low to BUFEN Low rdhbufh T83 RD High to BUFEN High bufldatv T84 BUFEN ...
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Switching Characteristics INTER-LERIC BUS OUTPUT TIMING Symbol Number ircoh T101 IRC Output High Time ircol T102 IRC Output Low Time ircoc T103 IRC Output Cycle Time actndapkena T104 ACTNd Active to PKEN Active (Note 1) actnolireol T105 ACTN ...
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AC Timing Test Conditions All specifications are valid only if the mandatory isolation is employed and all differential signals are taken AUI side of the pulse transormer Input Pulse Levels (TTL CMOS) Input Rise and ...
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... Physical Dimensions inches (millimeters) Plastic Chip Carrier (V) Order Number DP83955AV NS Package Number V84A 52 ...
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Physical Dimensions inches (millimeters) (Continued) Plastic Quad Flatpak Order Number DP83956AVLJ NS Package Number VLJ100A 53 ...
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... Hong Kong Ltd 49) 0-180-530 85 86 13th Floor Straight Block a Ocean Centre 5 Canton Rd 49) 0-180-530 85 85 Tsimshatsui Kowloon a Tel ( 49) 0-180-532 78 32 Hong Kong a 49) 0-180-532 93 58 Tel (852) 2737-1600 a Tel ( 49) 0-180-534 16 80 Fax (852) 2736-9960 a National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 ...