DP83955AV National Semiconductor, DP83955AV Datasheet - Page 29

• Manufacturer Part Number: DP83955AV
• Description: IC CTRLR RIC REPEATER 100-PQFP
• Manufacturer: National Semiconductor
• Series: LERIC™r

Specifications of DP83955AV

• Controller Type: LitE Repeater Interface Controller
• Voltage - Supply: 5V
• Current - Supply: 250mA
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Interface: -
• Other names: *DP83955AV

5 0 Functional Description
5 4 DESCRIPTION OF HARDWARE CONNECTION
FOR CASCADING
5 4 1 DP89355 on the Inter-LERIC Bus
When considering the hardware interface the Inter-LERIC
bus may be viewed as consisting of three groups of signals
1 Port Arbitration chain namely ACKI and ACKO These
2 Simultaneous drive and sense signals namely ACTN
3 Drive or sense signals (i e IRE IRD IRC and COLN)
5 4 2 DP83956 Using the Inter-RIC Bus
When considering the hardware interface the Inter-LERIC
bus may be viewed as consisting of three groups of signals
1 Port Arbitration chain namely ACKI and ACKO These
2 The need for simultaneous sense and drive capabilities
3 Drive or sense signals i e IRE IRD IRC and COLN
operation with external bus transceivers makes it neces-
signals are either used as point-to-point links or with ex-
ternal arbitration logic In both cases the load on these
signals will not be large so that the on-chip drivers are
adequate
and ANYXN Potentially these signals may be driven by
multiple devices It should be noticed that due to the
nature of these signals transceivers cannot be imple-
mented for the purpose of cascading however bench
evaluation indicates that LERICs can be cascaded to-
gether as long as the total load capacitance is 100 pF or
less
Only one device asserts these signals at any instance in
time The unidirectional nature of information transfer on
the IRE IRD IRC and COLN signals means a LERIC is
either driving these signals or receiving them from the
bus but not both at the same time Thus a single bidirec-
tional input output pin is adequate for each of these sig-
nals
signals are either used as point to point links or with
external arbitration logic In both cases the load on these
signals will not be large so that the on-chip drivers are
adequate
on the ACTN and ANYXN signals and the desire to allow
sary for these bus signals to each have a pair of pins
one to drive the bus and the other to sense the bus The
Inter-LERIC bus on the DP83956 has been designed to
connect LERICs together directly or via external bus
transceivers The latter is advantageous in large repeat-
ers When external bus transceivers are used they must
be open collector open drain to allow wire-ORing of the
signals
Only one device asserts these signals at any instance in
time The unidirectional nature of information transfer on
the IRE IRD IRC and COLN signals means a LERIC is
either driving these signals or receiving them from the
(Continued)
29
5 5 PROCESSOR AND DISPLAY INTERFACE
The processor interface pins which include the data bus
address bus and control signals actually perform three op-
erations which are multiplexed on these pins These opera-
tions are
1 The MLOAD Operation which performs a power up ini-
2 Display Update Cycles which are refresh operations for
3 Processor Access Cycles which allow
These three operations are described below
MLOAD Operation
The MLOAD Operation is a hardware initialization procedure
performed at power on It loads vital device configuration
information into on chip configuration registers In addition
to its configuration function the MLOAD pin is the LERIC’s
reset input When MLOAD is low all of the LERIC’s repeater
timers state machines and segment partition logic are re-
set
The MLOAD Operation may be accomplished by attaching
the appropriate set of pull up and pull down resistors to the
data and register address pins to assert logic high or low
signals onto these pins and then providing a rising edge on
the MLOAD pin as is shown in Figure 5-8 The mapping of
chip functions to the configuration inputs is shown in Table
5-2 Such an arrangement may be performed using a simple
resistor capacitor diode network Performing the MLOAD
Operation in this way enables the configuration of a LERIC
that is in a simple repeater system (one without a proces-
sor)
Alternatively in a complex repeater system the MLOAD Op-
eration may be performed using a processor write cycle
This would require the MLOAD pin be connected to the
CPU’s write strobe via some decoding logic and included in
the processor’s memory map
tialization cycle upon the LERIC
updating the display LEDs
logic) to communicate with the LERIC’s registers
bus but not both at the same time Thus a single bidirec-
tional input output pin is adequate for each of these
signals When an external bus transceiver is used with
these signals the Packet Enable ‘‘PKEN’’ an output pin
of LERIC performs the function of a drive enable and
sense disable
FIGURE 5-8 MLOAD Operation
P’s (or simple
TL F 11240 – 14