DP83955AV National Semiconductor, DP83955AV Datasheet - Page 17

• Manufacturer Part Number: DP83955AV
• Description: IC CTRLR RIC REPEATER 100-PQFP
• Manufacturer: National Semiconductor
• Series: LERIC™r

Specifications of DP83955AV

• Controller Type: LitE Repeater Interface Controller
• Voltage - Supply: 5V
• Current - Supply: 250mA
• Mounting Type: Surface Mount
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Interface: -
• Other names: *DP83955AV

Figure 4-1
5 0 Functional Description
The IEEE 802 3 repeater specification details a number of
functions a repeater system must perform These require-
ments allied with a need for the implementation to be multi-
port strongly favors the choice of a modular design style In
such a design functionality is split between those tasks
common to all data channels and those exclusive to each
individual channel The LERIC much like the DP83950 RIC
follows this approach Certain functional blocks are replicat-
ed for each network attachment (also known as a repeater
port) and others are shared The following section briefly
describes the functional blocks in the LERIC
5 1 OVERVIEW OF LERIC FUNCTIONS
Segment Specific Block Network Port
As shown in the Block Diagram the segment specific blocks
consist of
1 One or more physical layer interfaces
2 A logic block required for performing repeater operations
This function is repeated 7 times in the LERIC (one for each
port) and is shown on the right side of the Block Diagram
The physical layer interfaces provided depends upon the
port under examination Port 1 has an AUI compliant inter-
face for use with AUI compatible transceiver boxes and ca-
ble Ports 2 to 7 may be configured for use with one of two
interfaces twisted pair or an external transceiver The for-
mer utilizes the LERIC’s on-chip 10BASE-T transceivers
the latter allows connection to external transceivers When
using the external transceiver mode the interface is AUI
compatible Although AUI compatible transceivers are sup-
ported the interface is not designed for use with an interface
cable thus the transceivers are necessarily internal to the
repeater equipment
Inside the port logic there are 3 distinct functions
1 The port state machine (PSM) is required to perform data
2 The port partition logic implements the segment parti-
3 The port status register reflects the current status of the
Shared Functional Blocks Repeater Core Logic
The shared functional blocks consist of the Repeater Main
Status Machine (MSM) and Timers a 32-bit Elasticity Buffer
PLL Decoder and Receive and Transmit Multiplexers
These blocks perform the majority of the operations needed
to fulfill the requirements of the IEEE repeater specification
When a packet is received by a port it is sent via the Re-
ceive Multiplexer to the PLL Decoder Notification of the
data and collision status is sent to the main state machine
via the receive multiplexer and collision activity status sig-
nals This enables the main state machine to determine the
source of the data to be repeated and the type of data to be
upon that particular segment This is known as the ‘‘port’’
logic since it is the access ‘‘port’’ the segment has to the
rest of the network
and collision repetition as described by the repeater
specification for example it determines whether this
port should be receiving from or transmitting to its net-
work segment
tioning algorithm This algorithm is defined by the IEEE
specification and is used to protect the network from
malfunctioning segments
port It may be accessed by a system processor to obtain
this status or to perform certain port configuration opera-
tions such as port disable and squelch level selection
17
transmitted The transmit data may be either the received
packet’s data field or a preamble jam pattern consisting of
a 1010
Associated with the main state machine are a series of tim-
ers These ensure various IEEE specification times (referred
to as the TW1 to TW6 times) are fulfilled
A repeater unit is required to meet the same signal jitter
performance as any receiving node attached to a network
segment Consequently a phase locked loop Manchester
decoder is required so that the packet may be decoded and
the jitter accumulated over the receiving segment eliminat-
ed The decode logic outputs data in NRZ format with an
associated clock and enable In this form the packet is in a
convenient format for transfer to other devices such as net-
work controllers and other LERICs via the Inter-LERIC bus
(described later) The data may then be re-encoded into
Manchester data and transmitted
Reception and transmission via physical layer transceiver
units causes a loss of bits in the preamble field of a data
packet The repeater specification requires this loss to be
compensated for To accomplish this an elasticity buffer is
employed to temporarily store bits in the data field of the
packet
The sequence of operation is as follows Soon after the
network segment receiving the data packet has been identi-
fied the LERIC begins to transmit the packet preamble pat-
tern (1010
preamble is being transmitted the Elasticity Buffer monitors
the decoded received clock and data signals (this is done
via the Inter-LERIC Inter-RIC bus as described later) When
the start of frame delimiter ‘‘SFD’’ is detected the received
data stream is written into the elasticity buffer Removal of
data from the buffer for retransmission is not allowed until a
valid length preamble pattern has been transmitted
Inter-LERIC Inter-RIC Bus Interface
The LERIC can be cascaded either to other LERICs or RICs
to facilitate the design of large multiport repeaters The split
of functions already described allows data packets and colli-
sion status to be transferred between multiple LERICs and
at the same time the multiple LERICs still behave as a sin-
gle logical repeater Since all LERICs in a repeater system
are identical and capable of performing any of the repetition
operations the failure of one LERIC will not cause the fail-
ure of the entire system This is an important issue in large
multiport repeaters
DP83955’s communicate via a specialized interface known
as the Inter-LERIC bus DP83956s can communicate with
other DP83956s and or DP83950s via the Inter-RIC bus
These allow the data packets to be transferred from the
receiving LERIC to the other LERICs in the system These
LERICs then transmit the data stream to their segments
Just as important as data transfer is the notification of colli-
sions occurring across the network The Inter-LERIC Inter-
RIC bus has a set of status lines capable of conveying colli-
sion information between LERICs to ensure their main state
machines operate in the appropriate manner
LED Interface
Repeater systems usually possess optical displays indicat-
ing network activity and the status of specific repeater oper-
ations The LERIC’s display update block provides the sys-
tem designer with a wide variety of indicators The display
bit pattern
) onto the other network segments While the